From: <ml...@ma...> - 2009-10-01 19:39:16
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Author: mlu Date: 2009-10-01 19:39:13 +0200 (Thu, 01 Oct 2009) New Revision: 2789 Modified: trunk/src/target/armv7a.c Log: ARMv7A: Report fault status registers when in Abort state Modified: trunk/src/target/armv7a.c =================================================================== --- trunk/src/target/armv7a.c 2009-09-30 23:20:52 UTC (rev 2788) +++ trunk/src/target/armv7a.c 2009-10-01 17:39:13 UTC (rev 2789) @@ -173,6 +173,26 @@ 0, 1, 96, NULL, 0, NULL, 0 }; +void armv7a_show_fault_registers(target_t *target) +{ + uint32_t dfsr, ifsr, dfar, ifar; + + /* get pointers to arch-specific information */ + armv4_5_common_t *armv4_5 = target->arch_info; + armv7a_common_t *armv7a = armv4_5->arch_info; + + armv7a->read_cp15(target, 0, 0, 5, 0, &dfsr); + armv7a->read_cp15(target, 0, 1, 5, 0, &ifsr); + armv7a->read_cp15(target, 0, 0, 6, 0, &dfar); + armv7a->read_cp15(target, 0, 2, 6, 0, &ifar); + + LOG_USER("Data fault registers DFSR: %8.8" PRIx32 + ", DFAR: %8.8" PRIx32, dfsr, dfar); + LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 + ", IFAR: %8.8" PRIx32, ifsr, ifar); + +} + int armv7a_arch_state(struct target_s *target) { static const char *state[] = @@ -206,6 +226,9 @@ state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); + if (armv4_5->core_mode == ARMV7A_MODE_ABT) + armv7a_show_fault_registers(target); + return ERROR_OK; } |