[Openocd-svn] r2666 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-04 07:20:45 +0200 (Fri, 04 Sep 2009)
New Revision: 2666

Modified:
   trunk/src/target/cortex_a8.c
   trunk/src/target/cortex_a8.h
Log:
Matt Hsu <ma...@0x...> Tidy up the bit-offset operation for DSCR register



Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-04 05:17:03 UTC (rev 2665)
+++ trunk/src/target/cortex_a8.c	2009-09-04 05:20:45 UTC (rev 2666)
@@ -166,7 +166,7 @@
 		retvalue = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 
@@ -175,7 +175,7 @@
 		retvalue = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	return retvalue;
 }
@@ -291,7 +291,7 @@
 		retval = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
-	while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
 	retval = mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -436,7 +436,7 @@
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << 0)) == 0);
+	} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
 
 	target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -535,7 +535,7 @@
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << 1)) == 0);
+	} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
@@ -582,7 +582,7 @@
 	/* Enable the ITR execution once we are in debug mode */
 	mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
-	dscr |= (1 << 13);
+	dscr |= (1 << DSCR_EXT_INT_EN);
 	retval = mem_ap_write_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
 

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-09-04 05:17:03 UTC (rev 2665)
+++ trunk/src/target/cortex_a8.h	2009-09-04 05:20:45 UTC (rev 2666)
@@ -67,6 +67,15 @@
 #define BRP_NORMAL 0
 #define BRP_CONTEXT 1
 
+/* DSCR Bit offset */
+#define DSCR_CORE_HALTED		0
+#define DSCR_CORE_RESTARTED 	1
+#define DSCR_EXT_INT_EN 		13
+#define DSCR_HALT_DBG_MODE		14
+#define DSCR_MON_DBG_MODE 		15
+#define DSCR_INSTR_COMP 		24
+#define DSCR_DTR_TX_FULL 		29
+
 typedef struct  cortex_a8_brp_s
 {
 	int used;