From: <oh...@ma...> - 2009-01-14 15:10:37
|
Author: oharboe Date: 2009-01-14 15:10:36 +0100 (Wed, 14 Jan 2009) New Revision: 1316 Modified: trunk/src/target/target/imx31.cfg Log: Alan Carvalho de Assis <ac...@gm...> small fix to move us in the right direction. Modified: trunk/src/target/target/imx31.cfg =================================================================== --- trunk/src/target/target/imx31.cfg 2009-01-13 14:26:19 UTC (rev 1315) +++ trunk/src/target/target/imx31.cfg 2009-01-14 14:10:36 UTC (rev 1316) @@ -45,14 +45,14 @@ # SDMA_BYPASS - disables SDMA - # # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register -jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID # No IDCODE for this TAP jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0 # Per section 40.17.1, table 40-85 the IR register is 4 bits # But this conflicts with Diagram 6-13, "3bits ir and drs" -jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SDMATAPID +jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0xf -expected-id $_SDMATAPID set _TARGETNAME [format "%s.cpu" $_CHIPNAME] target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME |