[Openocd-svn] r1312 - trunk/src/target/target

[<oh...@ma...>]

Author: oharboe
Date: 2009-01-09 14:04:37 +0100 (Fri, 09 Jan 2009)
New Revision: 1312

Modified:
   trunk/src/target/target/imx31.cfg
Log:
wip

Modified: trunk/src/target/target/imx31.cfg
===================================================================
--- trunk/src/target/target/imx31.cfg	2009-01-09 11:44:01 UTC (rev 1311)
+++ trunk/src/target/target/imx31.cfg	2009-01-09 13:04:37 UTC (rev 1312)
@@ -1,7 +1,8 @@
 # imx31 config
 #
-# NB! Does not work yet. Work in progress
 
+reset_config trst_and_srst
+
 if { [info exists CHIPNAME] } {	
    set  _CHIPNAME $CHIPNAME    
 } else {	 
@@ -17,19 +18,24 @@
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
+   set _CPUTAPID 0x07b3601d
 }
 
+if { [info exists SDMATAPID ] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x2190101d
+}
+
 #========================================
 # The "system jtag controller" 
 # IMX31 reference manual, page 6-28 - figure 6-14
 if { [info exists SJCTAPID ] } {
    set _SJCTAPID $SJCTAPID
 } else {
-   set _SJCTAPID 0xffffffff
+   set _SJCTAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 00 irmask 0x0 -expected-id $_SJCTAPID
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
 
 # The "SDMA" - <S>mart <DMA> controller debug tap
 # Based on some IO pins - this can be disabled & removed
@@ -38,28 +44,19 @@
 #    SJC_MOD - controls multiplexer - disables ARM1136
 #    SDMA_BYPASS - disables SDMA    - 
 #  
-if { [info exists SDMATAPID ] } {
-   set _SDMATAPID $SDMATAPID
-} else {
-   set _SDMATAPID 0xffffffff
-}
-# Per section 40.17.1, table 40-85 the IR register is 4 bits
-# But this conflicts with Diagram 6-13, "3bits ir and drs"
-jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SJCTAPID
-
-# The ARM11 core tap
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0xffffffff
-}
 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e irmask 0x1f -expected-id $_SJCTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
 
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
 
-jtag_nsrst_delay 500
-jtag_ntrst_delay 500
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SDMATAPID
 
 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
- 
+
+
+proc power_restore {} { puts "Sensed power restore. No action." } 
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }