Re: [Openocd-development] adapter_khz ...

[Laurent G. <lau...@am...>]

David Brownell wrote:
> On Thursday 25 March 2010, Laurent Gauch wrote:
>   
>>> JTAG and SWD share key signals though ... on both adapter and target
>>> sides.  Lots of boards have a single JTAG/SWD connector.
>>>
>>>
>>>   
>>>       
>> Yes, lot of boards, but not all boards. Amontec has customers having 
>> JTAG daisy chains of more than 10 devices (target) on the same boards.
>>     
>
> That's irrelevant for dual-mode (JTAG and/or SWD) ..
>
>   
>> Also, that's why we have target script and board script. At board level, 
>> if you have 3 targets in the JTAG chain, with max frequency of 15MHz 
>> 30MHz 60MHz, the max frequency of the JTAG chain will be around 15Mhz. 
>> Also, this is why we have max frequency specified in the JTAG BSDL file. 
>> But not all targets comes with BSDL. Result, we have to specify JTAG max 
>> frequency to any target script.
>>     
>
> Actually by that argument -- too! -- the frequency is board-specific,
> not target-specific.
>
>
>   
>> SWD cannot support more than one device on the same port !
>> JTAG + RTCK is actually not really used in JTAG daisy chain structure.
>>     
>
> That depends entirely on the board layout.  I've seen boards with a
> simple CPLD set up to make RCLK work on multiple targets.  The key is
> is clock voting .... the RCLK signal going back to the adapter combines
> signals from multiple targets.
>
> ISTR there's a link to a TI webpage with the VHDL for that in the User's
> GUide, probably in the FAQ entry for adaptive clocking.
>
>   
Yes I know and we have done the 'RTCK CPLD Switch' exercise one time 
last year in the Amontec Labs.
But it is not so easy to manage and this is why I wrote :

'JTAG + RTCK is actually *not really used* in JTAG daisy chain structure'

Laurent
  http://www.amontec.com 

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