#86 Changes to MOSFET's parameters

[Kostas Karalis]

Good evening and happy new year team,

I am creating the circuit with the netlist in the end of this ticket. The bigger picture is that I want to make multiple simulations with different transistor sizing, to calculate the specific current of each one of them. Specifically, I have a problem with the change of the parameters of my mosfets. When I set them manually, in the circuit, I get a different result than what occurs when I change them from ngspice code. As I saw from the latest manual of ngspice, chapter 13.5.3 and from the chapter 27.1, I made the code below. In the .pdf that I uploaded to you, I have the code and some screenshots, of my results. Also, when I ran "show" in ngspice shell, I saw that it has a "_ mfactor" and an "m" parameter; if I want to change the multiplicity parameter, which of these 2 should I modify?

Thank you for your time!

" sch_path: /foss/designs/analog-circuit-design/xschem/my_projects/nmos_extract_Ispec.sch
.subckt nmos_extract_Ispec
XM1 net3 net1 net2 GND sg13_lv_nmos w=1u l=1u ng=1 m=1
VSB net2 GND 0
Vgb net1 GND 0.6
Vdb net3 GND 1.2
**** begin user architecture code

.lib cornerMOSlv.lib mos_tt
.save all
.probe I(vdb)
.control
let mos_width = 2.0u ;UNCOMMENT LINE
let mos_length = 2.0u ;UNCOMMENT LINE
alter @n.xm1.nsg13_lv_nmos[w] = $&mos_width ;UNCOMMENT LINE
alter @n.xm1.nsg13_lv_nmos[l] = $&mos_length ;UNCOMMENT LINE
;while mos_width <= 10.0u
; alter @n.XM1.nsg13_lv_nmos[w] = $mos_width
; set length = 0.13u
; while mos_length <= 10.0u
; alter @n.XM1.nsg13_lv_nmos[l] = $mos_length
DC VSB -0.4 1.2 0.1 TEMP -10 80 15
set filetype=ascii
set wr_vecnames
; print @n.XM1.nsg13_lv_nmos
; wrdata nmos_extract_Ispec.txt vdb#branch current_temperature mos_length mos_width
wrdata nmos_extract_Ispec.tsv vdb#branch ; mos_length mos_width
set appendwrite
set nounits
write nmos_extract_Ispec.raw
; end
; let mos_length = mos_length + 1u
; end
; let mos_width = mos_width + 1u
;end
.endc
.END

** end user architecture code
.ends
.GLOBAL GND
.end"

[Dietmar Warning]

The structure of your testbench is unusual and wrong: control section and swept voltage source inside subckt.
Please break down your testcase to a much simpler spice netlist to demonstrate your problem. Schematics and PDF doc's will not help.
Attached is a similar script for gm-Id plot. Perhaps it helps.

[Kostas Karalis]

Hello Mr. Dietmar ,

The file that you attached, was very helpful. I adjusted my code, and it worked correctly (as it is in the end of this message). I tried to change the structure of my testbench so it is simpler (both for me and for someone who tries to read it), but I don't know if I changed something substantially (I will try to keep up). Thanks again.

" sch_path: /foss/designs/analog-circuit-design/xschem/my_projects/nmos_extract_Ispec.sch
.subckt nmos_extract_Ispec
XM1 D G S GND sg13_lv_nmos w='mos_w' l='mos_l' ng=1 m=1
VSB S GND 0
Vgb G GND 0.6
Vdb D GND 1.2
**** begin user architecture code

.lib cornerMOSlv.lib mos_tt
.param mos_l = 0.13u mos_w = 0.13u
.save all

.control
let mos_length = 0.13u
let mos_width = 0.13u
while mos_width <= 10u
let mos_length = 0.13u
while mos_length <= 10u
alterparam mos_w = $&mos_width
alterparam mos_l = $&mos_length
reset
DC VSB -0.4 1.2 0.05 TEMP -40 125 15
set filetype=ascii
set wr_vecnames
wrdata nmos_extract_Ispec.tsv vdb#branch mos_width mos_length
set appendwrite
set nounits
write nmos_extract_Ispec.raw
let mos_length = mos_length + 0.5u
end
let mos_width = mos_width + 0.5u
end
.endc
.END

** end user architecture code
.ends
.GLOBAL GND
.end"