ngspice / Support Requests / #46 Convergence issues (gmin stepping failed)

Christoph - 2019-10-21

fortgot the .cir

Last edit: Christoph 2019-10-21

gmin.cir

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Christoph - 2019-10-21

ngspice version:
ngspice-31 : Circuit level simulation program
Creation Date: Oct 6 2019 15:17:58

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Maybe one of you can help me out. Thank you.

We also need siov.lib .

-marcel

Hmm... a classical NR problem: pretty persistent oscillation between two extremes (look at the node voltages now and previous).

-marcel

Wait a minute, this is not a varistor -- it limits no matter the device terminal voltage amplitude ... Where did I make a mistake in this translation?

Congratulations to LTspice -- it can simulate this strangeness (but for two missing braces on the subcircuit call line).

-marcel

.title gmin schematic

.func LIMIT(x, y, z) {min(max(x, min(y, z)), max(z, y))}

V0 In  0  dc=1 pulse(-0.01k 0.01k 10n 100n 100n 300n 600n)
R2 Out In  100
R1 Out 0   100
XRvar  Out 0   S14K300

.save @v0[i] @r2[i] @r1[i] V(In) V(Out)
.tran 1ns 800ns 0 1ns

.subckt siov 1 2   t=1 c=1pf l=1nh b1=1 b2=1 b3=0 b4=0
r_series  1 3 100u
l_series  3 4 {l}
v_i_sense 4 5 0v
h_i_sense 6 0 v_i_sense 10k
r_i_sense 6 0 1g
e_var     5 2 value={t*(    
 +             pwr(10, b1+b2*(log10( limit(v(6), 1m, 100g))-4) +
 +             b3*exp(-log10( limit(v(6), 1m, 100g)) + 4)  +
 +             b4*exp( log10( limit(v(6), 1m, 100g)) - 4)) -
 +             pwr(10, b1+b2*(log10(-limit(v(6),-100g,-1m))-4) +
 +             b3*exp(-log10(-limit(v(6),-100g,-1m)) + 4)  +
 +             b4*exp( log10(-limit(v(6),-100g,-1m)) - 4)) +
 +             limit((v(6)*1k*v(7)),-v(7),v(7)) )}

c_par  4   2  {c}
e_sw   7   0  value={pwr(10,(b1+b2*(-7)+b3*exp(+7)+b4*exp(-7)))}
r_sw   7   0  1g
r_sw2  5   2  1MEG
.ends SIOV

.subckt s14k300 1 2 tol=0
x1 1 2 siov  t={1+tol/100} c=300pf l=12.0nh b1=2.7733130 b2=0.0306573 b3=-0.0004977 b4=0.0042636
.ends S14K300

* .control
*   listing e
*   run
*   write gmin.raw
*   plot V(out) @R1[i]
*   quit
* .endc

.end

Last edit: marcel hendrix 2019-10-24

varistor.png

The following is an input file made of the circuit after parsing it with the ngspice inpcom parser (only slight modified to get the subcircuit calls right), as delivered by debug-out1.txt:

gmin schematic
* translated by ngspice inpcom parser, slightly modified
* o.k. with LTSPICE
.include "D:\Software\Spice\various\SIOV.LIB"
.param gmin=1e-12
.global gnd
.subckt siov 1 2 params: t=1 c=1pf l=1nh b1=1 b2=1 b3=0 b4=0
r_series 1 3 100u
l_series 3 4 {l}
v_i_sense 4 5 0v
h_i_sense 6 0 v_i_sense 10k
r_i_sense 6 0 1g
e_var 5 2 e_var_int1 0 1
be_var e_var_int1 0 v= ({t}) * ( ( abs (   1.0000000000e+01 ) ** ( ({b1}) + ({b2}) * ( log10 ( ( min ( max ( ( v(6) ) ,   1.0000000000e-03 ) ,   1.0000000000e+11 ) ) )  -4.0000000000e+00 ) + ({b3}) * exp ( - log10 ( ( min ( max ( ( v(6) ) ,   1.0000000000e-03 ) ,   1.0000000000e+11 ) ) ) +   4.0000000000e+00 ) + ({b4}) * exp ( log10 ( ( min ( max ( ( v(6) ) ,   1.0000000000e-03 ) ,   1.0000000000e+11 ) ) )  -4.0000000000e+00 ) ) ) - ( abs (   1.0000000000e+01 ) ** ( ({b1}) + ({b2}) * ( log10 ( - ( min ( max ( ( v(6) ) , (  -1.0000000000e+11 ) ) , (  -1.0000000000e-03 ) ) ) )  -4.0000000000e+00 ) + ({b3}) * exp ( - log10 ( - ( min ( max ( ( v(6) ) , (  -1.0000000000e+11 ) ) , (  -1.0000000000e-03 ) ) ) ) +   4.0000000000e+00 ) + ({b4}) * exp ( log10 ( - ( min ( max ( ( v(6) ) , (  -1.0000000000e+11 ) ) , (  -1.0000000000e-03 ) ) ) )  -4.0000000000e+00 ) ) ) + ( min ( max ( ( ( v(6) *   1.0000000000e+03 * v(7) ) ) , ( - v(7) ) ) , ( v(7) ) ) ) )
c_par 4 2 {c}
e_sw 7 0 e_sw_int1 0 1
be_sw e_sw_int1 0 v= ( abs (   1.0000000000e+01 ) ** ( ( ({b1}) + ({b2}) * (  -7.0000000000e+00 ) + ({b3}) * exp ( +   7.0000000000e+00 ) + ({b4}) * exp (  -7.0000000000e+00 ) ) ) )
r_sw 7 0 1g
.ends
.subckt s14k300 1 2 params: tol=0
* .SUBCKT SIOV 1 2 PARAMS: T=1 C=1pF L=1nH B1=1 B2=1 B3=0 B4=0
x1 1 2 siov T={1+tol/100} C=300pf L=12.0nh B1=2.7733130 B2=0.0306573 B3={-0.0004977} B4=0.0042636
.ends
v0 in 0 dc 1 ac 0 pulse(0 2k 10n 100n 100n 300n)
r2 out in 100
r1 out 0 100
xrvar out 0 s14k300 tol=0
.save @v0[i]
.save @r2[i]
.save @r1[i]
.save v(in)
.save v(out)
.tran 1ns 1000ns
.end

Same result as with the original file, LTSPICE o.k., ngspice not.

We have to spend some time looking at the op calculation.

Holger Vogt - 2019-10-24

And we should re-check if the derivatives of the pwr (**) function are o.k.

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Francesco Lannutti - 2019-10-22

Hi all,
if a varistor is a variable resistance, I think we are suffering from non-linearity issue here...
You need to smooth more the variations of that resistance, IMHO.

Thank you,
Fra

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marcel hendrix - 2019-10-24

The following is an input file made of the circuit after parsing it with the
ngspice inpcom parser (only slight modified to get the subcircuit calls right),
as delivered by debug-out1.txt:

Feeding this preparsed NGSPICE cir file to LTspice is possible, and LTspice
converges (maybe Holger did this already, I am not sure). Therefore the
observed differences are indeed in NGSPICE's simulation engine.

However, in LTspice when I use the following slightly modified V0 source:

v0 in 0 dc 1 ac 0 pulse(-700 2k 10n 100n 100n 300n 800n)

... LTspice also crashes.

BTW, again the output is in no way resembling a varistor (e.g. the
clipping boundaries are asymmetric).

-marcel
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Convergence issues (gmin stepping failed)

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#46 Convergence issues (gmin stepping failed)

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