ngspice-users — The users mailing list for ngspice (general discussions).

[Ngspice-users] Which OS is OK for ngspice?

[Wei F. <wei...@gm...>]

Hello, I am a beginner of ngspice.
I compiled and installed ngspice-rework-15 on Redhat Enterprise Linux
4, but met a lot of problems during simulation.

Can anybody recommand some edition of Linux on which ngspice can work
normally? Also your version of ngspice ?

Thanks!

[Ngspice-users] Re: about saving analysis results

[Wei F. <wei...@gm...>]

Hi, I have a solution.

Use the following command avoiding getting into the ngspice shell:

$ ngspice -b your_netlist.sp -r result.raw
After that, all the simulation results are saved into the rawfile "result.r=
aw"
using binary format.

If you want to see the results, get into the ngspice shell:
$ ngspice
ngspice 1 -> load result.raw



2005/10/30, ngs...@li...
<ngs...@li...>:
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> Today's Topics:
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>   1. (no subject) (Stephen Henry)
>   2. about interpolation (Yoichiro Niitsu)
>
> --__--__--
>
> Message: 1
> Date: Sat, 29 Oct 2005 11:17:40 +0000
> From: Stephen Henry <ste...@gm...>
> To: ngs...@li...
> Subject: [Ngspice-users] (no subject)
> Reply-To: ngs...@li...
>
> ------=3D_Part_8324_6651505.1130584660756
> Content-Type: text/plain; charset=3DISO-8859-1
> Content-Transfer-Encoding: quoted-printable
> Content-Disposition: inline
>
> Hi all,
>
> I'm quite new to SPICE and I'm having some difficulty getting results out=
 o=3D
> f
> it. I have the following circuit (in the file inv.sp):
>
> Simple CMOS Inverter
>
> VCC 4 0 5
> VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS
> RB 1 2 10K
> Q1 3 2 0 Q1
> RC 3 4 1K
> .MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF
> .DC VIN 0 5 0.1
> .TRAN 1NS 100NS
> .END
>
> and I run this in ngspice using the command:
>
> ngspice -i inv.sp
>
> I type "run", to run the simulation, and then "quit" to leave the simulat=
or=3D
> .
>
> The problem i'm having is that I would like to save the plots of the
> analysis. I type "save" and/or "save all" and every time when I leave the
> simulation, ngspice reports "Warning: the following plots haven't been
> saved" ... and so on. Does anyone know how I can get data out of the
> simulator so I can plot some graphs of my simulation.
>
> Thanks,
>
> Stephen
>
> BTW: does anyone know where I can get some documentation on using spice
> (along with examples). I've been using the spice3 documentation as found =
on
> the ngspice website, but, as you can see, I obviously still having some
> problems. Any ideas?
>
> ------=3D_Part_8324_6651505.1130584660756
> Content-Type: text/html; charset=3DISO-8859-1
> Content-Transfer-Encoding: quoted-printable
> Content-Disposition: inline
>
> <div id=3D3D"mb_0">Hi all,<br>
> <br>
> I'm quite new to SPICE and I'm having some difficulty getting results
> out of it. I have the following circuit (in the file inv.sp):<br>
> <br>
> Simple CMOS Inverter<br>
> <br>
> VCC 4 0 5<br>
> VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS<br>
> RB 1 2 10K<br>
> Q1 3 2 0 Q1<br>
> RC 3 4 1K<br>
> .MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF<br>
> .DC VIN 0 5 0.1<br>
> .TRAN 1NS 100NS<br>
> .END<br>
> <br>
> and I run this in ngspice using the command:<br>
> <br>
> ngspice -i inv.sp<br>
> <br>
> I type &quot;run&quot;, to run the simulation, and then &quot;quit&quot; =
to=3D
>  leave the simulator.<br>
> <br>
> The problem i'm having is that I would like to save the plots of the
> analysis. I type &quot;save&quot; and/or &quot;save all&quot; and every t=
im=3D
> e when I leave
> the simulation, ngspice reports &quot;Warning: the following plots haven'=
t
> been saved&quot; ... and so on. Does anyone know how I can get data out o=
f
> the simulator so I can plot some graphs of my simulation.<br>
> <br>
> Thanks,<br>
> <br>
> Stephen<br>
> <br>
> BTW: does anyone know where I can get some documentation on using spice
> (along with examples). I've been using the spice3 documentation as
> found on the ngspice website, but, as you can see, I obviously still
> having some problems. Any ideas?<br>
>
> </div>
>
> ------=3D_Part_8324_6651505.1130584660756--
>
>
> --__--__--
>
> Message: 2
> From: "Yoichiro Niitsu" <yoi...@r0...>
> To: <ngs...@li...>
> Date: Sun, 30 Oct 2005 03:38:51 +0900
> Subject: [Ngspice-users] about interpolation
> Reply-To: ngs...@li...
>
> Dear Developers,
>
> Do you still use ft_polyfit() for interpolation of plot or fourier
> transformation?
> That function is not a dedicated routine for interpolation but just a sim=
ple
> solver of
> simulteneous equations, I think.
> If that is still used, I recommend to get the real interpolation routine,
> eg. cubic
> spline, from Netlib, GSL, etc.
>
> Regards,
> Y. Niitsu
>
>
>
>
> --__--__--
>
> _______________________________________________
> Ngspice-users mailing list
> Ngs...@li...
> https://lists.sourceforge.net/lists/listinfo/ngspice-users
>
>
> End of Ngspice-users Digest
>

[Ngspice-users] about interpolation

[Yoichiro N. <yoi...@r0...>]

Dear Developers,

Do you still use ft_polyfit() for interpolation of plot or fourier
transformation?
That function is not a dedicated routine for interpolation but just a simple
solver of
simulteneous equations, I think.
If that is still used, I recommend to get the real interpolation routine,
eg. cubic
spline, from Netlib, GSL, etc.

Regards,
Y. Niitsu

[Ngspice-users] (no subject)

[Stephen H. <ste...@gm...>]

Hi all,

I'm quite new to SPICE and I'm having some difficulty getting results out o=
f
it. I have the following circuit (in the file inv.sp):

Simple CMOS Inverter

VCC 4 0 5
VIN 1 0 PULSE 0 5 2NS 2NS 2NS 30NS
RB 1 2 10K
Q1 3 2 0 Q1
RC 3 4 1K
.MODEL Q1 NPN BF 20 RB 100 TF .1NS CJC 2PF
.DC VIN 0 5 0.1
.TRAN 1NS 100NS
.END

and I run this in ngspice using the command:

ngspice -i inv.sp

I type "run", to run the simulation, and then "quit" to leave the simulator=
.

The problem i'm having is that I would like to save the plots of the
analysis. I type "save" and/or "save all" and every time when I leave the
simulation, ngspice reports "Warning: the following plots haven't been
saved" ... and so on. Does anyone know how I can get data out of the
simulator so I can plot some graphs of my simulation.

Thanks,

Stephen

BTW: does anyone know where I can get some documentation on using spice
(along with examples). I've been using the spice3 documentation as found on
the ngspice website, but, as you can see, I obviously still having some
problems. Any ideas?

RE: [Ngspice-users] NGSPICE Transient Analysis question

[A & T C. <ac...@sp...>]

Ok, one more question...the codemodel I am writing takes a current as
input and outputs a voltage.  I would like to tie multiple iterations of
the codemodel together in a simulation in series basically.  My
codemodel works as expected for a single iteration.  However, it does
not work as expected for multiple models in a series.  Anyone have any
ideas as to why?  Any generic rules for doing this kind of thing in
NGSPICE?

Tony


-----Original Message-----
From: ngs...@li...
[mailto:ngs...@li...] On Behalf Of Stefan
Jones
Sent: Friday, October 21, 2005 11:28 AM
To: ngs...@li...
Subject: Re: [Ngspice-users] NGSPICE Transient Analysis question

A & T Carver wrote:

>All,
>
>I am creating a codemodel using NGSPICE, and I have noticed during a
>transient analysis, NGSPICE will backup in time.  The current time
point
>will be before the previous.  Can someone explain why/when that would
>happen?
>  
>
After each timestep is computed spice does some error checking to see if

the timestep is small enough for the changes which happened in the
circuit.

If the timestep is not small enough, it is made smaller and the last 
timestep is resimulated.

 From a device point of view; after each timestep which is accepted by 
the error checking, DEVaccept is called. So the device knows then that 
the timestep is ste in stone.

Stefan


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Re: [Ngspice-users] Regarding the code

[Anil K. A. <ani...@ho...>]

Hai Victor,
                Thanks for ur replay. Please send me the report to my 
official mail id.

al...@un...

Thankyou

Regards,
anil




>From: Victor Bourenkov <vi...@ty...>
>Reply-To: ngs...@li...
>To: ngs...@li...
>Subject: Re: [Ngspice-users] Regarding the code
>Date: Wed, 26 Oct 2005 10:31:07 +0100 (IST)
>
>Hi Anil,
>
>I can send you my dissertation on implementation of table lookup models in
>SPICE. Part of it (overview of circuit simulation) briefly explains how 
>circuit
>simulators work. If you want is sent to you, please provide me with your 
>real
>e-mail address (not hotmail).
>In any case, the SPICE manual, available from UCB (Berkeley), is good 
>start.
>Also the following books may be of help:
>
>@book{m1,
>    author = {William J. McCalla},
>    edition = {1},
>    publisher = {Kluwer Academic Publishers Group},
>    title = {{Fundamentals of Computer-Aided Circuit Simulation}},
>    year = {1988}
>}
>
>@book{m2,
>    author = {Juin J. Liou},
>    publisher = {Artech House},
>    address = {London},
>    title = {{Advanced Semiconductor Device Physics and Modelling}},
>    pages = {255-272},
>    year = {1994}
>}
>
>@book{m3,
>    author = {Ron M. Kielkowski},
>    edition = {1},
>    publisher = {McGraw Hill},
>    address = {USA},
>    title = {{Inside Spice: overcoming the obstacles of circuit 
>simulation}},
>    year = {1994}
>}
>
>@book{m4,
>    author = {Albert Paul Malvino},
>    edition = {3},
>    publisher = {Tata McGraw-Hill},
>    address = {New Dehli, India},
>    title = {{Electronic Principles}},
>    year = {1988}
>}
>
>@book{m5,
>    author = {Dileep A. Divekar},
>    publisher = {Kluwer Academic Publishers Group},
>    title = {{FET Modeling for Circuit Simulation}},
>    year = {1988}
>}
>
>@book{m6,
>    author = {Andrei Vladimirescu},
>    publisher = {J. Wiley and Sons},
>    address = {New York, USA},
>    pages = {12-15},
>    title = {{The SPICE Book}},
>    year = {1994}
>}
>
>Cheers,
>Victor
>
> >
> > Hai,
> >
> >         Does anybody have the documentation on architecture of SPICE.  I
> > like to know the path, how the circuit is converted into data 
>structures.
> >
> > If you any link for the documentatio. Please let me know.
> >
> > Hope someone can help me.
> >
> > Thank you
> >
> > Regards,
> > anil
> >
>
>
>
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Re: [Ngspice-users] Regarding the code

[Gregor B. <gr...@tf...>]

Hi all, 

Am Dienstag, 25. Oktober 2005 19:59 schrieb Anil Kumar Ale:
>         Does anybody have the documentation on architecture of SPICE.  I
> like to know the path, how the circuit is converted into data structures.

The algorithms are described here:

@techreport{Nagel:M520,
    Author = {Laurence W. Nagel},
    Title = {SPICE2: A computer program to simulate semiconductor circuits},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1975},
    Number = {UCB/ERL M520}
}

Although a little outdated the following are a great help in reading the code. 
This should really be part of the source.

@techreport{Quarles:M89/44,
    Author = {T. Quarles},
    Title = {The SPICE3 Implementation Guide},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Number = {UCB/ERL M89/44}
}

@techreport{Quarles:M89/45,
    Author = {T. Quarles},
    Title = {Adding Devices to SPICE3},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {1989},
    Number = {UCB/ERL M89/45}
}

As far as I know they are only available in printed form, if at all.

I anybody know where to get them machine readable, please let me know.



Regards,
Gregor

Re: [Ngspice-users] Regarding the code

[Victor B. <vi...@ty...>]

Hi Anil,

I can send you my dissertation on implementation of table lookup models in 
SPICE. Part of it (overview of circuit simulation) briefly explains how circuit 
simulators work. If you want is sent to you, please provide me with your real 
e-mail address (not hotmail).
In any case, the SPICE manual, available from UCB (Berkeley), is good start. 
Also the following books may be of help:

@book{m1,
   author = {William J. McCalla},
   edition = {1},
   publisher = {Kluwer Academic Publishers Group},
   title = {{Fundamentals of Computer-Aided Circuit Simulation}},
   year = {1988}
}

@book{m2,
   author = {Juin J. Liou},
   publisher = {Artech House},
   address = {London},
   title = {{Advanced Semiconductor Device Physics and Modelling}},
   pages = {255-272},
   year = {1994}
}

@book{m3,
   author = {Ron M. Kielkowski},
   edition = {1},
   publisher = {McGraw Hill},
   address = {USA},
   title = {{Inside Spice: overcoming the obstacles of circuit simulation}},
   year = {1994}
}

@book{m4,
   author = {Albert Paul Malvino},
   edition = {3},
   publisher = {Tata McGraw-Hill},
   address = {New Dehli, India},
   title = {{Electronic Principles}},
   year = {1988}
}

@book{m5,
   author = {Dileep A. Divekar},
   publisher = {Kluwer Academic Publishers Group},
   title = {{FET Modeling for Circuit Simulation}},
   year = {1988}
}

@book{m6,
   author = {Andrei Vladimirescu},
   publisher = {J. Wiley and Sons},
   address = {New York, USA},
   pages = {12-15},
   title = {{The SPICE Book}},
   year = {1994}
}

Cheers,
Victor

> 
> Hai,
> 
>         Does anybody have the documentation on architecture of SPICE.  I 
> like to know the path, how the circuit is converted into data structures.
> 
> If you any link for the documentatio. Please let me know.
> 
> Hope someone can help me.
> 
> Thank you
> 
> Regards,
> anil
> 

Re: [Ngspice-users] Regarding the code

[Dietmar W. <wa...@da...>]

Anil Kumar Ale schrieb:

>
> Hai,
>
>        Does anybody have the documentation on architecture of SPICE.  
> I like to know the path, how the circuit is converted into data 
> structures.
>
> If you any link for the documentatio. Please let me know.
>
> Hope someone can help me.
>
> Thank you
>
> Regards,
> anil
>
> _________________________________________________________________
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>
>
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> Ngs...@li...
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>
>
Ask your Professor - Anil.

[Ngspice-users] Regarding the code

[Anil K. A. <ani...@ho...>]

Hai,

        Does anybody have the documentation on architecture of SPICE.  I 
like to know the path, how the circuit is converted into data structures.

If you any link for the documentatio. Please let me know.

Hope someone can help me.

Thank you

Regards,
anil

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RE: [Ngspice-users] if else syntax

[Dominique M. <dom...@ho...>]

It is the u and uramp functions that you can use in the non-linear source. 
They are easy to use but for the clarity of your subcircuit, it can be 
necessary to slit your B source definition in 2 or 3 lines.

B1 1 0 v=(expression with u(v(7)))(expression 1)
B2 2 0 v=(expression with u(v(7)))(expression 2)
B3 3 0 v=v(1)+v(2)

Dominique


>From: Matt Flax <flatmax@Matt.Flax>
>Reply-To: ngs...@li...
>To: Ngs...@li...
>Subject: [Ngspice-users] if else syntax
>Date: Thu, 22 Sep 2005 22:18:13 +1000
>
>Hello,
>
>I have to implement a function which is ill-defined at a particular
>voltage. I can think up a way to implement it using an 'if' 'else'
>methodology, but am not sure if it is possible ???
>
>I was wondering whether it is possible to define a non-linear source
>like so :
>Bsource 1 0 v= if (v(7)==0) then 1 else 2
>
>Probably not!
>If not then ... can anyone suggest a different way to acheive the same
>thing ?
>
>thanks
>Matt
>--
>http://www.flatmax.org
>
>Public Projects :
>http://sourceforge.net/search/?type_of_search=soft&words=mffm
>
>
>
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Re: [Ngspice-users] Piece-wise Linear Source causes ERROR

[Dominique M. <dom...@ho...>]

The "out of memory" said at the program was failing because your computer 
doesn't have enough RAM. If it is true, the system was really slow and at 
the end, you get this error message.

You must have very little memory in your box and if you want to do some real 
simulation, not just one like this with 4 components, i can only suggest you 
to buy some extra memory. Considere also at you must have enough with disk 
space if you want to save the simulation. It is very easy to get enormous 
data file of a few hundred of MB with transiet simulation.

Dominique

>From: Meinrad Hell <mei...@t-...>
>Reply-To: ngs...@li...
>To: ngs...@li...
>Subject: Re: [Ngspice-users] Piece-wise Linear Source causes ERROR
>Date: Tue, 27 Sep 2005 20:18:07 +0200
>
>Hi,
>
>Just for your information,
>checked your circuit.
>I am using ngspice 1.5 and it worked .
>
>must be something else,
>
>sorry for the limited information.
>
>Meinrad
>
>
>
>
>On Thu, 2005-09-08 at 14:25 +1000, Matt Flax wrote:
> > Hi,
> >
> > That circuit works for me !
> >
> > I am using release 17 ...
> >
> > On Thu, Sep 08, 2005 at 11:30:35AM +0800, Wei Fei wrote:
> > > my circuit netlist is:
> > >
> > > ********************************************
> > > Vin 2 0 pwl(0 0 10u 1)
> > > R2 3 2 1k
> > > C2 3 0 1n
> > > R3 3 0 10k
> > >
> > > .options list node post
> > > .tran 0.1u 10u
> > >
> > > .save all
> > > .end
> > > ********************************************
> > >
> > > when I simulate it with ngspice,
> > > I get:
> > >
> > > doAnalyses: out of memory
> > > run simulation aborted
> > >
> > > Does anyone know how to solve this problem?
> > > Thanks.
> > >
> > >
> > > -------------------------------------------------------
> > > SF.Net email is Sponsored by the Better Software Conference & EXPO
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>
>
>
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RE: [Ngspice-users] NGSPICE Transient Analysis question

[A & T C. <ac...@sp...>]

So I can check DEVaccept in the code to make sure the timestep was
accepted.  If it isn't I assume T(1) remains the same with a shorter
timestep to T(0)???

Tony

-----Original Message-----
From: ngs...@li...
[mailto:ngs...@li...] On Behalf Of Stefan
Jones
Sent: Friday, October 21, 2005 11:28 AM
To: ngs...@li...
Subject: Re: [Ngspice-users] NGSPICE Transient Analysis question

A & T Carver wrote:

>All,
>
>I am creating a codemodel using NGSPICE, and I have noticed during a
>transient analysis, NGSPICE will backup in time.  The current time
point
>will be before the previous.  Can someone explain why/when that would
>happen?
>  
>
After each timestep is computed spice does some error checking to see if

the timestep is small enough for the changes which happened in the
circuit.

If the timestep is not small enough, it is made smaller and the last 
timestep is resimulated.

 From a device point of view; after each timestep which is accepted by 
the error checking, DEVaccept is called. So the device knows then that 
the timestep is ste in stone.

Stefan


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Power Architecture Resource Center: Free content, downloads,
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_______________________________________________
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[Ngspice-users] Help me Regarding the Code

[Anil K. A. <ani...@ho...>]

Hai all,

         I have some problem in source code. Can anyone help me, how ngspice 
converts the netlist into datastructure,how it converts into equation and 
how it choose algorithm to give output? Can you help what are the program 
file in the source code. And how can i find it.

Hope anyone can help me

Thank you,

Regards,
anil

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Re: [Ngspice-users] NGSPICE Transient Analysis question

[Victor B. <vi...@ty...>]

Hi Tony,

Well, if you haven't accidentally discovered a flaw in some dimension of 
time-space continuum, then the reason may be that circuit analysis failed to 
converge during "previous" time step. The usual procedure for the simulator in 
this case is to decrease the value of time step and try again.
Thus the simulation may go through time as illustrated:
0 ms -> 10ms -> 20 ms -> 30 ms (failed) -> 25 ms (failed) -> 22.5 ms -> 25 ms -> 
and so on

How does this "backup in time" manifest itself?

Cheers,
Victor

> 
> All,
> 
> I am creating a codemodel using NGSPICE, and I have noticed during a
> transient analysis, NGSPICE will backup in time.  The current time point
> will be before the previous.  Can someone explain why/when that would
> happen?
> 
> Thanks,
> Tony
> 

Re: [Ngspice-users] NGSPICE Transient Analysis question

[Stefan J. <ste...@mu...>]

A & T Carver wrote:

>All,
>
>I am creating a codemodel using NGSPICE, and I have noticed during a
>transient analysis, NGSPICE will backup in time.  The current time point
>will be before the previous.  Can someone explain why/when that would
>happen?
>  
>
After each timestep is computed spice does some error checking to see if 
the timestep is small enough for the changes which happened in the circuit.

If the timestep is not small enough, it is made smaller and the last 
timestep is resimulated.

 From a device point of view; after each timestep which is accepted by 
the error checking, DEVaccept is called. So the device knows then that 
the timestep is ste in stone.

Stefan

[Ngspice-users] NGSPICE Transient Analysis question

[A & T C. <ac...@sp...>]

All,

I am creating a codemodel using NGSPICE, and I have noticed during a
transient analysis, NGSPICE will backup in time.  The current time point
will be before the previous.  Can someone explain why/when that would
happen?

Thanks,
Tony

[Ngspice-users] RE:

[noid <no...@li...>]

[Ngspice-users] Comparator convergence problem

[<jo...@so...>]

Hello, I'm new to ngspice (an spice in general,) but was trying my hands  
on modelling a pwm-amplifier (which I'm also new to, I'm a modest 2. year  
EE-student.) Anyways, a pwm-amplifier needs a comparator so I search  
around the net and found one from Maxim which had spice models (not  
specific for ngspice.) However when I try to use it, the simulation  
doesn't converge. Below is my spice netlist and the Maxim macromodel.  
(Btw. I've tried with op-amp models from TI and NatSemi as replacement,  
however the TI one didn't converge and the NatSemi only resulted in noise  
(I later noticed that it wasn't suited for use as a comparator.) The  
models were, respectively; LM318 and LM7131A.) If anyone can spot any  
blindingly obvious errors or give some general tips for helping  
convergence problems, please shout out! (Btw. it's not a complete PWM-amp.)

Ran with the following command:
# ngspice -r pwmamp.raw -b pwmamp.spi

pwmamp.spi:
------------
PWM Amplifier

.OPTION ITL4=50 RELTOL=0.001

.INCLUDE komponenter/MAX999.FAM

VTri            0  1    PULSE(-1V, 1V, 0.0, 500ns, 500ns, 0.0, 1us)
VTest           0  2    SIN(0.0, 0.2V, 10kHz)
VComp           0  3    DC 5V
XComp           4  0  1  2  3   MAX999
RL              4  0    1kOhm


.TRAN 100ns 100us

.END


komponenter/MAX999.FAM:
------------------------
* MAX999 MACROMODEL
* ------------------------------
* Revision 0, 12/2004
* ------------------------------
* MAX999 is a low-power, ultra-high-speed comparator with internal
* hysteresis.
* ------------------------------
* Connections
*   1  = Q
*   2  = GND
*   3  = IN+
*   4  = IN-
*   5  = VCC
**************************
.SUBCKT MAX999 1 2 3 4 5
* NOTE: INCLUDE
*            .OPTION ITL4=50 RELTOL=0.001
*                                        TO ENHANCE CONVERGENCE.
X1 3 4 5 2 2 1 6 MAX999CMP
.ENDS
**************************

**************************
.SUBCKT MAX999CMP   1 2 3 4 300 433 483
***
vshortle 352 300 0v
f101    3  9 v1 1
Iee100   7  400 dc 100.0E-6
q101    9  20  7 qin
Q2    8  21  7 qin
Q3    9  8  399 qmo
Q4    8  8  399 qmi
VMB 400 4 0V
VPB 399 3 0V
***================
VIN1 2 23 .95
VIN2 1 25 .95
***
IPSUP 3 0 6.5ma
*INSUP 0 4 11ma
***
EHYST 23 20 POLY(1) 0 60 0 1
VS2 21 25 0V
.model qin NPN(Is=800.0E-18 Bf=3.33)
.model qmi PNP(Is=800.0E-18 Bf=1002)
.model qmo PNP(Is=800.0E-18 Bf=1000 Cjc=1E-15 Tr=3.3E-9)
.MODEL PMOS PMOS
*(VTO=-1.7 KP=1.8E-3)
e1   10  4  3  9  2
v1   10 11 dc 0
q5    5 11  44 qoc
vshift 44 4 0v
*clamps output, Q5 collector load.
R55 3 5 1meg
DP5 5 3 DP
DP6 4 5 DP
***============= Hysterisis section
GH 0 51 32 101 1E-6
ECM 101 0 3 4 0.5
RCM 101 0 10MEG
****==============COMPARATOR POINT FOR CREATING LOGIC OUTPUT, +-1, hi,lo.
RH1 3 51 1E11
RH2 4 51 1E11
DP1 51 52 DP
DP2 53 51 DP
VP1 52 0 1V
VP2 53 0 -1V
***=================
IHYST 55 0 -1E-9
*GENERATES 1MV OF HYST. TO MIMIC SMOOTH TRANSITION.
RREF 55 0 1E6
*LOGIC OUTPUT, NODE 60 ALTERS THE POLARITY, SO 55 SHOULD ALWAYS BE POS.
GMULT 60 0 POLY(2) 51 0 55 0 0 0  0 0 1E-6
RMULT 60 0 1E6
*================
*EH 3 98 3 4 0.5
VVIRTUAL 98 0 0V
G12 98 32 5 0 7.04E-3
R15 98 32 140
*========================
.model qoc NPN(Is=800.0E-18 Bf=181 Cjc=1E-15 Tf=42e-12 Tr=2E-9)
.MODEL DX  D(Is=800.0E-18)
.MODEL DP D(N=0.001)
*=======================
***== MODELS USED ==***
.MODEL DX2 D(IS=1E-15 n=0.001)
*** **********************************
*** **********************************
VCONNECT 302 32 0V
* AND1
* 302, 312 is the input, output is 333.
RN1 302 303 1MEG
DA1 305 330 DP
DA2 300 305 DP
RA2 304 305 1MEG
EA1 304 300 POLY(1) 302 303 0 10
***
RN10 312 303 1MEG
DA10 315 330 DP
DA12A 300 315 DP
RA12 314 315 1MEG
EA11 314 300 POLY(1) 312 303 0 -10
*-10 COMPLIMENTS LE, SO LOW IS TRANSPARENT
***
GAMULT 300 331 POLY(2) 305 300 315 300  0 0 0 0 1E-6
RAMULT 331 300 1G
DA5 331 330 DP
DA6 300 331 DP
EOA 332 300 331 300 1
ROA 332 333 100
***
* AND2
* 352, 362 is the input, output is 383.
RN12 352 303 1MEG
ILE 352 300 -20UA
DA12 355 380 DP
DA22 300 355 DP
RA22 354 355 1MEG
EA12 354 300 POLY(1) 352 303 0 -10
*-10 COMPLIMENTS LE, SO LOW IS TRANSPARENT
***
RN102 362 303 1MEG
DA102 365 380 DP
DA122 300 365 DP
RA122 364 365 1MEG
EA112 364 300 POLY(1) 362 303 0 10
***
GAMULT2 300 381 POLY(2) 355 300 365 300  0 0 0 0 1E-6
RAMULT2 381 300 1G
DA52 381 330 DP
DA62 300 381 DP
EOA2 382 300 381 300 1
ROA2 382 383 100
***
* OR1
* 402,412 are the inputs, output is 433
RO1 402 403 1MEG
VO14 403 300 1.4V
VO1 430 300 5V
DO1 405 430 DP
DO2 300 405 DP
RO2 404 405 1MEG
EO1 404 300 POLY(1) 402 403 0 10
***
RO10 412 403 1MEG
DO10 415 430 DP
DO12 300 415 DP
RO12O 414 415 300
EO11 414 300 POLY(1) 412 403 0 10
***
GOADD1 300 431 POLY(2) 405 300 415 300 0 1E-6 1E-6
ROADD 431 300 1G
DO5 431 3 DP
DO6 300 431 DP
EOO 432 300 431 300 1
ROO 432 433 125
* OR2
* 452,462 are the inputs, output is 488
RO12 452 403 1MEG
VO12 480 300 5V
DO12O 455 480 DP
DO22 300 455 DP
RO22 454 455 1MEG
EO12 454 300 POLY(1) 452 403 0 10
***
RO102 462 403 1MEG
DO102 465 480 DP
DO122 300 465 DP
RO122 464 465 300
EO112 464 300 POLY(1) 462 403 0 10
***
GOADD12 300 481 POLY(2) 455 300 465 300 0 1E-6 1E-6
ROADD2 481 300 1G
DO52 481 3 DP
DO62 300 481 DP
EOO2 482 300 481 300 1
ROO2 482 483 125
* INVERTER1
*INPUT 602, OUTPUT  605
RIN1 602 303 1MEG
DIA1 605 630 DP
DIA2 300 605 DP
vi1 630 300 5v
RIA2 604 605 10k
EIA1 604 300 POLY(1) 602 303 0 -10
* INVERTER2
*INPUT 612, OUTPUT 615
RIN12 612 303 1MEG
DIA12 615 640 DP
DIA22 300 615 DP
vi12 640 300 5v
RIA22 614 615 10k
EIA12 614 300 POLY(1) 612 303 0 -10
* INVERTER3
*INPUT 622, OUTPUT 625
RIN13 622 303 1MEG
DIA13 625 650 DP
DIA23 300 625 DP
vi13 650 300 5v
RIA23 624 625 10k
EIA13 624 300 POLY(1) 622 303 0 -10
*** ********BIASING****************
*** *******************************
VA14 303 300 1.4V
VA1 330 300 5V
*VDGND 300 0 0V
***
* CONNECTIONS *********************
VSH1 605 362 0V
VSH2 312 352 0V
VSH3 333 402 0V
VSH4 383 462 0V
VSH5 433 622 0V
VSH6 625 452 0V
VSH7 483 612 0V
VSH8 615 412 0V
VSH9 302 602 0V
.ENDS
**************************

Best,
Jon Øyvind Kjellman

[Ngspice-users] Ngspice package for Slackware 10.2 available.

[R S A. M. <rsa...@sa...>]

Hello users,

I have prepared Ngspice 17 package for Slackware 10.2. It is available for 
download at www.linuxpackages.net.

Enjoy!

Anand

Re: [Ngspice-users] Problems with ngspice and ngnutmeg

[Andreas U. <a_...@gm...>]

Hi Alex,

I didn't try it with Cygwin, but it works fine when I compile the 
ngspice package (ng-spice-rework-17) as a native Windows program.

Andreas

Alex Roman wrote:
> Hi,
> 
> I'm using the Cygwin environment to compile ngspice.
> 
> I did this:
> 
> ./configure --enable-xspice --enable-cider --without-windows --with-x 
> --prefix=/usr/local
> make
> make install
> 
> It compiled fine.
> 
> I tried testing ngspice and ngnutmeg with the following file:
> 
> --1.cir--
> CAPACITOR CHARGE CURVE
> 
> VCC 1 0 DC 12
> R1 1 2 100
> C1 2 0 4.7UF
> 
> .TRAN 1MS 500MS
> 
> .PLOT TRAN V(2)
> 
> .END
> --1.cir--
> 
> Then I did:
> ngspice -r 1.raw -b 1.cir
> ngnutmeg 1.raw
> 
> Then in ngnutmeg I did:
> plot V(1) - showed up fine, correctly
> 
> However, doing:
> plot V(2)
> 
> gave me a window showing a black box and two blank rectangles at the 
> right (the buttons). ngnutmeg froze then and it was using up a lot of CPU.
> 
> Is this a bug, or is it my problem? If so, what am I doing wrong?
> 
> 
> Thanks,
> Alex Roman.
> 
> 
> -------------------------------------------------------
> This SF.Net email is sponsored by:
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> https://lists.sourceforge.net/lists/listinfo/ngspice-users
> 
> 

[Ngspice-users] Problems with ngspice and ngnutmeg

[Alex R. <all...@ya...>]

Hi,

I'm using the Cygwin environment to compile ngspice.

I did this:

./configure --enable-xspice --enable-cider --without-windows --with-x --prefix=/usr/local
make
make install

It compiled fine.

I tried testing ngspice and ngnutmeg with the following file:

--1.cir--
CAPACITOR CHARGE CURVE

VCC 1 0 DC 12
R1 1 2 100
C1 2 0 4.7UF

.TRAN 1MS 500MS

.PLOT TRAN V(2)

.END
--1.cir--

Then I did:
ngspice -r 1.raw -b 1.cir
ngnutmeg 1.raw

Then in ngnutmeg I did:
plot V(1) - showed up fine, correctly

However, doing:
plot V(2)

gave me a window showing a black box and two blank rectangles at the right (the buttons). ngnutmeg froze then and it was using up a lot of CPU.

Is this a bug, or is it my problem? If so, what am I doing wrong?


Thanks,
Alex Roman.

Re: [Ngspice-users] Piece-wise Linear Source causes ERROR

[Meinrad H. <mei...@t-...>]

Hi,

Just for your information,
checked your circuit. 
I am using ngspice 1.5 and it worked .

must be something else,

sorry for the limited information.

Meinrad




On Thu, 2005-09-08 at 14:25 +1000, Matt Flax wrote:
> Hi,
> 
> That circuit works for me !
> 
> I am using release 17 ...
> 
> On Thu, Sep 08, 2005 at 11:30:35AM +0800, Wei Fei wrote:
> > my circuit netlist is:
> > 
> > ********************************************
> > Vin 2 0 pwl(0 0 10u 1)
> > R2 3 2 1k
> > C2 3 0 1n
> > R3 3 0 10k
> > 
> > .options list node post
> > .tran 0.1u 10u
> > 
> > .save all
> > .end
> > ********************************************
> > 
> > when I simulate it with ngspice,
> > I get:
> > 
> > doAnalyses: out of memory
> > run simulation aborted
> > 
> > Does anyone know how to solve this problem? 
> > Thanks.
> > 
> > 
> > -------------------------------------------------------
> > SF.Net email is Sponsored by the Better Software Conference & EXPO
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> > Agile & Plan-Driven Development * Managing Projects & Teams * Testing & QA
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> > _______________________________________________
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> > https://lists.sourceforge.net/lists/listinfo/ngspice-users
> 

RE: [Ngspice-users] Can't Instantiate subcircuit

[Steve T. <sc...@gm...>]

Ngspice-rework-17 does support the PARAMS syntax, but only if it is compiled
with the proper options set (--enable-params I believe) and only if the
feature is turned on at run time (with the "set numparams" directive).

Steve

-----Original Message-----
From: ngs...@li...
[mailto:ngs...@li...] On Behalf Of Stuart
Brorson
Sent: Tuesday, September 27, 2005 6:07 AM
To: ngs...@li...
Subject: Re: [Ngspice-users] Can't Instantiate subcircuit

> ngspice 15 -> source rect_completa.cir
> 
> Circuit: *Rectificador de onda completa con SCR's
> 
> Too few parameters for subcircuit type "mcr703at4" (instance: xty_1)

[ . . . . . .]

> My Spice source file is:
> 
> * Rectificador de onda completa con SCR's
> *----------------------------------------------
> *=09NGSPICE - NETLIST
> *---------------------------------------------------------------------
> -----
> .INCLUDE MCR703AT4.LIB
> *                 SIN(Voffset Amp. Freq. Delay damp.Factor)
> Vin 1 2 AC 170.0 SIN(0.0     1.0  60    0     0)
> *         PULSE V1  V2   Td    Tr    Tf    Pw  Periodo
> 
> *MCR703AT4 anode gate cathode
> XTY_1 1 4 3 MCR703AT4
> XTY_2 2 5 3 MCR703AT4
> XTY_3 0 5 1 MCR703AT4
> XTY_4 0 4 2 MCR703AT4

Here's the beginning of the .subckt in the lib you reference:

.SUBCKT MCR703AT4 anode gate cathode PARAMS:
+ Vdrm=100v     Vrrm=100v     Idrm=10u
+ Ih=5ma        dVdt=10e6
+ Igt=25ua      Vgt=0.8v
+ Vtm=2.2v      Itm=8.2
+ Ton=2u        Toff=15u

I am not sure that ngspice supports this PARAMS syntax, which must be PSpice
specific.  Ngspice will definately support regular SPICE3 .subckt syntax as
documented atL

http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec2.html#2.4

Stuart


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Re: [Ngspice-users] Can't Instantiate subcircuit

[<sd...@cl...>]

> ngspice 15 -> source rect_completa.cir
> 
> Circuit: *Rectificador de onda completa con SCR's
> 
> Too few parameters for subcircuit type "mcr703at4" (instance: xty_1)

[ . . . . . .]

> My Spice source file is:
> 
> * Rectificador de onda completa con SCR's
> *----------------------------------------------
> *=09NGSPICE - NETLIST
> *--------------------------------------------------------------------------
> .INCLUDE MCR703AT4.LIB
> *                 SIN(Voffset Amp. Freq. Delay damp.Factor)
> Vin 1 2 AC 170.0 SIN(0.0     1.0  60    0     0)
> *         PULSE V1  V2   Td    Tr    Tf    Pw  Periodo
> 
> *MCR703AT4 anode gate cathode
> XTY_1 1 4 3 MCR703AT4
> XTY_2 2 5 3 MCR703AT4
> XTY_3 0 5 1 MCR703AT4
> XTY_4 0 4 2 MCR703AT4

Here's the beginning of the .subckt in the lib you reference:

.SUBCKT MCR703AT4 anode gate cathode PARAMS:
+ Vdrm=100v     Vrrm=100v     Idrm=10u
+ Ih=5ma        dVdt=10e6
+ Igt=25ua      Vgt=0.8v
+ Vtm=2.2v      Itm=8.2
+ Ton=2u        Toff=15u

I am not sure that ngspice supports this PARAMS syntax, which must be
PSpice specific.  Ngspice will definately support regular SPICE3
.subckt syntax as documented atL

http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/sec2.html#2.4

Stuart