ngspice-devel — Ngspice development list (developers are here).

Re: [Ngspice-devel] Qucs-S v1.0.2 release

[Sourav C. <sou...@gm...>]

Dear all developers,
      I want to see the miller effect of mosfet. Anyone can give any
suggestion how to add the effect in the matrix of stamp?
With regards,

On Mon, Apr 24, 2023 at 4:58 PM Vadim Kuznetsov <ra...@gm...> wrote:

> Hello Qucs and Ngspice developers,
>
> I am glad to present a new Qucs-S v1.0.2 release. The packages and
> installation instructions could be found at the release page
> https://github.com/ra3xdh/qucs_s/releases/tag/1.0.2  Here is the summary
> of the new features:
>
>
>      * Added XSPICE flip-flop digital devices
>      * Added INDQ and CAPQ devices representing inductor and capacitor
> with Q-factor
>      * Added .LIB directive support
>      * Added SPICE entries for I and V file sources
>      * Added symbols for 4 and 5 terminal BJT device
>      * Improved Qt6 and MacOS compatibility
>
>
> Regards,
> Vadim Kuznetsov
>
>
> _______________________________________________
> Ngspice-devel mailing list
> Ngs...@li...
> https://lists.sourceforge.net/lists/listinfo/ngspice-devel
>

[Ngspice-devel] Qucs-S v1.0.2 release

[Vadim K. <ra...@gm...>]

Hello Qucs and Ngspice developers,

I am glad to present a new Qucs-S v1.0.2 release. The packages and 
installation instructions could be found at the release page 
https://github.com/ra3xdh/qucs_s/releases/tag/1.0.2  Here is the summary 
of the new features:


     * Added XSPICE flip-flop digital devices
     * Added INDQ and CAPQ devices representing inductor and capacitor 
with Q-factor
     * Added .LIB directive support
     * Added SPICE entries for I and V file sources
     * Added symbols for 4 and 5 terminal BJT device
     * Improved Qt6 and MacOS compatibility


Regards,
Vadim Kuznetsov

Re: [Ngspice-devel] Interest in Contributing to ngspice Development and Parameter Extraction

[Holger V. <hol...@un...>]

There is a Verilog-A model for organic transistors available at 
https://nanohub.org/publications/456/1.

I do not know if this model compiles with OpenVAF and thus can be used 
in ngspice. I also do not know anything about the quality of this model.

But you may give it a try.

[Ngspice-devel] Interest in Contributing to ngspice Development and Parameter Extraction

[liuyi <l1...@16...>]

Hello, ngspice Developers,



Thank you for your response. I will be working on parameter extraction and simulation in the near future, and if all goes well, I will bring my parameters to discuss related issues at the end of April. 


I was not familiar with the Verilog-A model before, but I will supplement my knowledge about this model while extracting parameters. 


In addition, I am still very interested and passionate about joining the ngspice development team, and I would appreciate any advice or suggestions on what I can do to contribute.




Thank you again for your help, and I look forward to hearing from you soon.




Best regards,

Fangxu Liu

Re: [Ngspice-devel] Interest in contributing to ngspice development for organic transistor simulation support

[Holger V. <hol...@un...>]

Dear Fangxu,

many thanks for your interest in ngscpice!

Supporting organic transistor simulation now does mean: supply a 
Verilog-A model of the organic transistor, compile it with OpenVAF, load 
the resulting shared library into ngspice, supply model parameters, and 
start simulation.

So no C coding is required. We need a Verilog-A model, test devices, 
measurements, parameter extraction and a lot of simulations for 
verification.

Please have a look at 
https://sourceforge.net/p/ngspice/mailman/ngspice-users/thread/DB8PR03MB58047A143575AFCA247B0BBBCBB49%40DB8PR03MB5804.eurprd03.prod.outlook.com/#msg37787906, 
which summarizes information on Verilog-A/OSDI/OpenVAF.

Holger

[Ngspice-devel] Interest in contributing to ngspice development for organic transistor simulation support

[l136665 <l1...@16...>]

Hello ngspice developers,

I am writing to express my interest in contributing to the development of ngspice with support for organic transistor simulation. I am currently a undergraduate student majoring in Electronic Science and Technology, and I have been studying the knowledge of organic transistors recently.

Although I have some C programming skills, I am not a computer science major, and reading through such a large codebase can be overwhelming. Therefore, I would like to ask if there are any documentation or code explanations related to ngspice that you could provide me with to help me better understand the project.

Furthermore, I have not found any SPICE models that support organic transistors. I was wondering if you have any knowledge on this topic, or if you could point me to resources that could help me learn more about it.

Thank you for your time and consideration. I look forward to your response.

Sincerely,

Fangxu Liu

[Ngspice-devel] Ngspice39 setting parameters for Verilog-A devices

[Vadim K. <ra...@gm...>]

Hello Ngspice developers,

I seems I have found a bug with new Verilog-A defined N device. The 
model parameters may be not accepted depending on the .MODEL statenent 
syntax. Parameter setting for the .MODEL has no effect if there is no 
space between model name and opening parentheses.

Here is a minimal example to reproduce this bug. See also discussion 
here: https://github.com/ra3xdh/qucs_s/issues/197#issuecomment-1365910190

File: RVA.va

`include "disciplines.vams"
`include "constants.vams"
module RVA(np,nn);
inout np,nn;
electrical np,nn;
parameter real R=1000.0;
analog begin
I(np,nn)<+V(np,nn)/R;
end
endmodule


File: test_rva.cir
* rva.cir
N1 1 0 rva1
.model rva1 RVA(R=100.0) * this line has no effect; R has default value 
1000Ohms
.model rva2 RVA (R=100.0) * R is set to 100Ohm if the space added
V1 1 0 dc 1
.control
pre_osdi rva.osdi
dc V1 0 1.0 0.1
plot -i(v1)
.endc


Regards,
Vadim Kuznetsov

[Ngspice-devel] Qucs-S 1.0.1 release

[Vadim K. <ra...@gm...>]

Hello Qucs and Ngspice developers,

I am glad to present a new Qucs-S v1.0.0 release. The packages and 
installation instructions could be found at the release page 
https://github.com/ra3xdh/qucs_s/releases/tag/1.0.1 Here is the summary 
of the new features:


   * Added support for Verilog-A defined devices using Ngspice+OpenVAF. 
Old Qucsator+ADMS
     workflow is marked as deprecated. Ngspice >=39 is required to 
support OpenVAF.
   * Implemented sweeping of variables with parameter sweep using Ngspice
   * Added possibility to build Qucs-S with Qt6 The -DWITH=QT6=ON option 
for cmake is required.
     The source code of the Qucs-S is Qt6 compatible now.
   * Simulator prefixes like "ngspice/" are not show anymore on plot 
traces if the plot contains data
     from only one simulator
   * Added TL071/TL072 opamp models
   * Added 555_timer.lib library containing the 555 timer model
   * Added extended BJT and Schottky diodes libraries

Regards,
Vadim Kuznetsov

Re: [Ngspice-devel] Bad syntax error for vccs from ltspice library

[Matt H. <hus...@gm...>]

Holger Vogt <hol...@un...> writes:

> did you make up your mind working on one of these issues (compatibility,
> OTA code model) ?

Hi Holger,

Thanks for the reminder email, as well as your previous email describing
what needs to be done. And, sorry for the delay in replying.

I'd like to work on it, but I haven't had a chance yet and I'm
unfortunately a bit tied up with other things at the moment. I'll keep
you posted if I get some time and make some progress, but unfortunately
it probably wouldn't be any time soon.

Matt

Re: [Ngspice-devel] Bad syntax error for vccs from ltspice library

[Holger V. <hol...@un...>]

Matt,

did you make up your mind working on one of these issues (compatibility, 
OTA code model) ?

Holger

Re: [Ngspice-devel] Bad syntax error for vccs from ltspice library

[Holger V. <hol...@un...>]

Matt,

many thanks for your offer to support ngspice development.

You will need a solid know-how of C coding for the two tasks envisioned.

Compatibility is dealt with in ngspice/src/frontend/inpcom.c. Especially 
the two functions pspice_compat() (lines 8524ff) and ltspice_compat() 
(lines 9565 ff) do the job during loading the netlist.

Concening the code model for the LTSPICE OTA, there is a basic framework 
available in ngspice git branch hv-ota-cm 
(https://sourceforge.net/p/ngspice/ngspice/ci/hv-ota-cm/tree/). You may 
have a look at my most recent commits to figure out the additions for a 
new code model OTA. A simple dc application is found in 
examples/xspice/various/ota-test1.cir. XSPICE code model source code is 
C plus Macros in cfunc.mod and ifspec.ifs in the respective directory 
ltota. A very similar code model, and a possible source of inspiration 
is the ilimit code model. Info about code models available is given in 
chapter 12, about code model coding in chapter 28 of the ngspice manual.

Still missing in the new OTA code model is the inclusion of voltage and 
current limits (including smooth transitions), the ac response and a 
thorough comparison with the LTSPICE model. Unfortunately the small 
signal noise is not implemented throughout all analog code models. This 
would be a major activity to enhance analog XSPICE, but would help us a 
lot. Noise simulation is similar to ac, so ac may serve as a template.

Holger

Re: [Ngspice-devel] Bad syntax error for vccs from ltspice library

[Matt H. <hus...@gm...>]

Thanks for the reply Holger.

Holger Vogt <hol...@un...> writes:

> ngspice does not understand the LTSPICE-specificG5 0 VILIM 3 4 table(1.6 
> 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m)
>
> An equivalent form for ngspice might be
> G6 0 VILIM  table {v(3,4)} = (1.6,6.5m) (1.8,6m) (2,6.2m) (2.4,8m)
> + (2.6,8m) (3.2,9m) (3.6,9m)

Would it be within scope to translate this to the ngspice-equivalent
form during include with the appropriate compatibility set (set
ngbehavior=...)? If so, would you mind directing me to the appropriate
part of the code base, so that I can look into adding it?

> More serious however is the usage of
> A2 0 N001 0 0 0 0 VDH 0 OTA
> + g=1.8m iout=100u Cout=56f Vlow=-1e308 Vhigh=1e308
>
> There is no equivalent ngspice replacement available. Currently this 
> LTSPICE model (family) cannot be simulated with ngspice.
>
> There is the idea to create a code model for this OTA, as it is used in 
> every LTC.lib model, but it is not yet done.

I can investigate this a bit. Has there been any existing effort on this
front that I can work off (or threads discussing it)? Any thoughts on
where/how to add this to the code would be helpful, as I'm a new
contributor to ngspice.

For anyone else coming across this there's a lot of info on the OTA
model on ltwiki:

https://ltwiki.org/?title=Undocumented_LTspice#OTA

Thanks,
Matt

Re: [Ngspice-devel] Bad syntax error for vccs from ltspice library

[Holger V. <hol...@un...>]

ngspice does not understand the LTSPICE-specificG5 0 VILIM 3 4 table(1.6 
6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m)

An equivalent form for ngspice might be
G6 0 VILIM  table {v(3,4)} = (1.6,6.5m) (1.8,6m) (2,6.2m) (2.4,8m)
+ (2.6,8m) (3.2,9m) (3.6,9m)

More serious however is the usage of
A2 0 N001 0 0 0 0 VDH 0 OTA
+ g=1.8m iout=100u Cout=56f Vlow=-1e308 Vhigh=1e308

There is no equivalent ngspice replacement available. Currently this 
LTSPICE model (family) cannot be simulated with ngspice.

There is the idea to create a code model for this OTA, as it is used in 
every LTC.lib model, but it is not yet done.

[Ngspice-devel] Bad syntax error for vccs from ltspice library

[Matt H. <hus...@gm...>]

Hello,

I'm attempting to perform a simulation that includes an LTC6752 subckt
that I took from the LTspice library. This subcircuit is causing a bad
syntax error. The line that causes it is

G5 0 VILIM 3 4 table(1.6 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m)

The error I see is

$ ngspice file2.cir
******
** ngspice-37 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2022, The ngspice team.
** Please get your ngspice manual from http://ngspice.sourceforge.net/docs.html
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html
** Creation Date: Tue May 17 10:02:30 UTC 2022
******

Note: Compatibility modes selected: ps lt

Error: bad syntax in line 55
  g5 0 vilim  poly(1) 3 4 table(1.6 6.5m 1.8 6m 2 6.2m 2.4 8m 2.6 8m 3.2 9m 3.6 9m)

ERROR: fatal error in ngspice, exit(1)

Is this a syntax error? If so, is there another way to achieve the same
effect?

I'm also attaching the actual ltc6752 model file in case that's useful.

Thanks
Matt

[Ngspice-devel] The Introduction of Chunqiao

[<cql...@ho...>]

Hi,

I am Chunqiao Li, from Shanghai, China. I am a Ph.d candidate in Fudan University. My major is microelectronics. I am interested in SPICE simulation. Happy to join the development team!

Sincerely,

Chunqiao



cql...@ho...

[Ngspice-devel] AMS / mixed types on wires

[Kevin C. <cam...@gm...>]

For anyone interested in adding mixed types on wires to VHDL/SV or
co-simulation, here's a proposal I have for IEEE P1800 -

https://docs.google.com/document/d/1PYPo_ZAiOtVXl53TDIBxyPwWoXFiwSpSYHCl3LPexXU/edit?usp=drivesdk

One of the drivers for this is bridging SystemC-AMS and SV, but given the
low probability of success at P1800, maybe the SC-AMS guys can be steered
to QUCS.

Kev.

On Sun, Oct 30, 2022, 3:40 PM Vadim Kuznetsov <ra...@gm...> wrote:

> Hello Qucs and Ngspice developers,
>
> I am glad to present a new Qucs-S v1.0.0 release. The packages and
> installation instructions could be found at the release page
> https://github.com/ra3xdh/qucs_s/releases/tag/1.0.0 Here is the summary
> of the new features:
>
>
> * Added basic support for logic gates simulation (Ngspice >= 38) required
> * Added possibility to set engineering notation (like 1k, 1M, etc.) for
> numbers on diagrams
> * Added symbol preview and search feature for component library in main
> windows
> * Backported qucs-attenuator, qucs-transcalc and qucs-powercombining
> from Qucs-0.0.20
> * Added possibility to set dB units for Y-axis on diagrams from the
> diagram properties dialog
> * Backported advanced features for projects tree from Qucs-0.0.20
> * Show warning if schematic file name changed, but dataset/display file
> name are not updated
> * Revised examples tree (by Tom Hajjar); legacy Ngspice-incompatible
> examples
>    moved to examples/qucsator subdirectory
>
> Regards,
> Vadim Kuznetsov
>
>
> _______________________________________________
> Qucs-devel mailing list
> Quc...@li...
> https://lists.sourceforge.net/lists/listinfo/qucs-devel
>

[Ngspice-devel] Qucs-S 1.0.0 release

[Vadim K. <ra...@gm...>]

Hello Qucs and Ngspice developers,

I am glad to present a new Qucs-S v1.0.0 release. The packages and 
installation instructions could be found at the release page 
https://github.com/ra3xdh/qucs_s/releases/tag/1.0.0 Here is the summary 
of the new features:


* Added basic support for logic gates simulation (Ngspice >= 38) required
* Added possibility to set engineering notation (like 1k, 1M, etc.) for 
numbers on diagrams
* Added symbol preview and search feature for component library in main 
windows
* Backported qucs-attenuator, qucs-transcalc and qucs-powercombining 
from Qucs-0.0.20
* Added possibility to set dB units for Y-axis on diagrams from the 
diagram properties dialog
* Backported advanced features for projects tree from Qucs-0.0.20
* Show warning if schematic file name changed, but dataset/display file 
name are not updated
* Revised examples tree (by Tom Hajjar); legacy Ngspice-incompatible 
examples
   moved to examples/qucsator subdirectory

Regards,
Vadim Kuznetsov

Re: [Ngspice-devel] Reducing test times

[Holger V. <hol...@un...>]

Marco,

indeed a new makefile target would have been the most elegant way. 
Unfortunately I do not have much experience with setting up such things, 
so for now it is the configure flag --enable-shortcheck which 
concentrates checking to BSM3 and BSIM4 only, after some general test 
have been performed.

The fix is uploaded to ngspice git branch pre-master and tested with Cygwin.

Holger

[Ngspice-devel] Qucs-S 0.0.24 release

[Vadim K. <ra...@gm...>]

Hello Qucs and Ngspice developers,

I am glad to present the Qucs-S 0.0.24 release. It contains a number of
important new features and two new simulation types:

* S-parameter simulation with Ngspice/Xyce backend
* FFT analysis with Ngspice backend

The download links could found at the release page
https://github.com/ra3xdh/qucs_s/releases/tag/0.0.24

Regards,
Vadim

Re: [Ngspice-devel] Reducing test times

[Marco A. <mar...@gm...>]

On 26.06.2022 11:38, Holger Vogt wrote:
> Marco,
> 
> would it be o.k. to compile with a special configure flag 
> --enable-shortcheck to enable a shortened 'make check'?
> 
> Holger
> 


Hi Holger,
it will be fine.
On another software I package, they provide both something like

   make test
   make quicktest

and the latter is a subset of the overall test coverage

My current workaround for release 37 was to test only the bsim3 model.
In our cygport build tool

src_test() {
         # cd ${B}/ngshared
         # make -i check
         # cd ${B}/standard
         # make -i check
         cd ${B}/standard/tests/bsim3
         make -i check
}


Thanks
Marco

Re: [Ngspice-devel] Reducing test times

[Holger V. <hol...@un...>]

Marco,

would it be o.k. to compile with a special configure flag 
--enable-shortcheck to enable a shortened 'make check'?

Holger

[Ngspice-devel] Reducing test times

[Marco A. <mar...@gm...>]

  Hi Developers,

question/feature request

as on Cygwin the "fork" is a painfull crowling function,
the current "make check" is taking forever
specially when doing it 2 times, for the shared library also,
there is a way to reduce the amount of verification ?


In other softwares, that I pack for Cygwin there is
a short and full version of the tests to fullfill
this issue.

Regards
Marco Atzeri

Cygwin package maintainer for ngspice and more
https://repology.org/maintainer/marco.atzeri%40cygwin/feed-for-repo/cygwin

Re: [Ngspice-devel] Convergence issue ngspice-36+ pre-master

[Holger V. <hol...@un...>]

To blame is the somewhat strange diode model parameter value IKF=0. We 
are working on a solution.

Re: [Ngspice-devel] Convergence issue ngspice-36+ pre-master

[Holger V. <hol...@un...>]

The offending commit is

0c34ac019 ("use total current for diffcap calculation", 2022-01-15)

We will have to check it.

Holger

[Ngspice-devel] Convergence issue ngspice-36+ pre-master

[Vadim K. <ra...@gm...>]

Hello Ngspice developers,

it seems, I have found a convergence issue with ngspice-36+ the latest 
pre-master branch. The attached netlist could be simulated fine using 
the Ngspice-36. But the simulation fails with the message "GMIN stepping 
failed" when using Ngspice-36+. Is it a real convergence issue or do I 
have something wrong with the build options? Here are the failure 
message extracted from the full log:

Warning: Dynamic gmin stepping failed

Note: Starting true gmin stepping

doAnalyses: TRAN: Timestep too small; initial timepoint: trouble with 
dmod_d_1n4148_1-instance d_1n4148_1

The build options are the following:

configure --enable-xspice --enable-sp

It complains about the diode model. Unfortunately I didn't found the 
minimal example to reproduce this problem. You can find the full netlist 
below. It is auto-generated by Qucs-S. This schematic was simulated by 
previous Ngspice version without any problems and could be simulated 
also by Xyce, but fails when using the latest Ngspice-36+ from the 
"pre-master" branch.

Regards,

Vadim

* Qucs 0.0.23 /home/vvk/TRX_6Bands/revers_amp_coomon_base_wb.sch

.INCLUDE 
"/home/vvk/qucs_s_qt5/share/qucs-s/xspice_cmlib/include/ngspice_mathfunc.inc"

* Qucs 0.0.23 /home/vvk/TRX_6Bands/revers_amp_coomon_base_wb.sch

QT_2N2222_1 _net1 _net0 _net2 QMOD_T_2N2222_1 AREA=1.0 TEMP=26.85

.MODEL QMOD_T_2N2222_1 npn (Is=1e-14 Nf=1 Nr=1 Ikf=0.3 Ikr=0 Vaf=100 
Var=0 Ise=0 Ne=1.5 Isc=0 Nc=2 Bf=200 Br=3 Rbm=0 Irb=0 Rc=3 Re=1 Rb=10 
Cje=2.5e-11 Vje=0.75 Mje=0.33 Cjc=8e-12 Vjc=0.75 Mjc=0.33 Xcjc=1 Cjs=0 
Vjs=0.75 Mjs=0 Fc=0.5 Tf=4e-10 Xtf=3 Vtf=0 Itf=2 Tr=1e-7 Kf=0 Af=1 Ptf=0 
Xtb=0 Xti=3 Eg=1.11 Tnom=26.85 )

R1 0 _net0 680

R2 _net0 _net3 2.2K

C3 _net4 out 10N

C4 _net0 _net3 100N

L3 _net3 _net4 100u

R3 0 out 50

D_1N4148_1 _net5 _net1 DMOD_D_1N4148_1 AREA=1.0 Temp=26.85

.MODEL DMOD_D_1N4148_1 D (Is=2.22e-10 N=1.65 Cj0=4e-12 M=0.333 Vj=0.7 
Fc=0.5 Rs=0.0686 Tt=5.76e-9 Ikf=0 Kf=0 Af=1 Bv=75 Ibv=1e-6 Xti=3 Eg=1.11 
Tcv=0 Trs=0 Ttt1=0 Ttt2=0 Tm1=0 Tm2=0 Tnom=26.85 )

C1 0 _net5 100N

K1 L3 L4 0.99

L4 _net4 _net1 100u

R6 _net1 _net3 330

C5 in _net2 10N

R5 0 _net2 470

V1 _net6 0 DC 0

L1 _net5 _net6 100U

D_1N4148_2 _net7 _net3 DMOD_D_1N4148_2 AREA=1.0 Temp=26.85

.MODEL DMOD_D_1N4148_2 D (Is=2.22e-10 N=1.65 Cj0=4e-12 M=0.333 Vj=0.7 
Fc=0.5 Rs=0.0686 Tt=5.76e-9 Ikf=0 Kf=0 Af=1 Bv=75 Ibv=1e-6 Xti=3 Eg=1.11 
Tcv=0 Trs=0 Ttt1=0 Ttt2=0 Tm1=0 Tm2=0 Tnom=26.85 )

L2 _net7 _net8 100U

V2 _net8 0 DC 12

C2 _net7 0 100N

R4 _net9 in 50

V3 _net9 0 DC 0 SIN(0 1M 8.867MEG 0 0 0) AC 1M

.control

echo "" > spice4qucs.cir.noise

echo "" > spice4qucs.cir.pz

tran 2.5e-9 5e-6 0

write revers_amp_coomon_base_wb_tran.txt v(in) v(out)

destroy all

reset

ac dec 80 0.01meg 15meg

let K = (v(out)/v(in))

let Kdb = db(v(out)/v(in))

write revers_amp_coomon_base_wb_ac.txt v(in) v(out) K Kdb

destroy all

reset

exit

.endc

.END