Re: [Ngspice-users] Verilog model effects the simulation run

[<mh...@ia...>]

On 2024-01-27 12:20, TM wrote:

> What are the reasons for the warnings? Can I improve something?

I can't read the (binary) osdi file, but from the other files
I suspect you placed an ideal voltage source across an ideal
inductor, clashing with the standard MNA formulation.

A (very small) series resistor can fix that.

-marcel