[Ngspice-users] Verilog model effects the simulation run

[TM <hm...@t-...>]

Hello,

I deal with Verilog models and I am testing a winding model (ideal 
electro-magnetic coupler), currently.

The creation of the OSDI-file for this model was successful. If I use 
this model in ngspice 42 I get the following warnings but the simulation 
case generated plausible results.

What are the reasons for the warnings? Can I improve something?

Attached I send the verilog file, the osdi file as well the ngspice file.

Best regards,
Thomas