#97 Set/Reset DFF XSPICE element

[Michael Köfinger]

Hi!
I wanted do perform a mixed-signal simulation using Yosis and XSpice elements as described in section 10.3.4 of the manual. I followed the linked example by Uros Platise. The flow seemed to work, but when I wanted to run a transient simulation, ngspice couldn't find a DFF with Set/Reset inputs. These elements are part of the primitive cells from the example code
https://github.com/Isotel/mixedsim/blob/master/models/yosys/prim_cells.v

module DFFSR(C, D, Q, S, R);
    input C, D, S, R;
    output reg Q;
    always @(posedge C, posedge S, posedge R)
        if (S)
            Q <= 1'b1;
        else if (R)
            Q <= 1'b0;
        else
            Q <= D;
endmodule

However, ngspice does only come with a DFF without S/R inputs. If I exclude those DFFSR from the prim_cells, the flow fails. I could for sure tweak the HDL source, but I think this is not a good way of handling this situation.

Is it possible to add such a cell to the list of basic XSpice elements?

Thanks!
Michael

[Giles Atkinson]

Rather than create a new FF, my approach would be to add synchronous SR inputs to the DFF. A recent change to XSPICE netlist parsing allows trailing "null" connections to be omitted, so no existing circuits would be harmed.

But since Yosys emits subcircuits for everything, you could just add it to prim_cells_ngspice.mod yourself: a subcircuit with some gates to combine D, S and R and a DFF.

If that does not work, please post example Verilog and circuit.

Edit: that is not right! The Verilog specifies an FF with asynchronous S/R, that XSPICE already has. So it can be simply:

.SUBCKT DFFSR C D Q S R
.model dff1 d_dff
Adff D C S R Q null dff1
.ENDS DFF

[Michael Köfinger]

Alright, I'm currently testing this, looks promising. I will contribute my changes to the Github repo once I'm done with testing :)

Edit: didn't see your edit before posting, I'll add this to the prim_cells_ngspice.mod and create a pull request.
Thanks!

[Giles Atkinson]

When you make the PR, may I suggest including another modification: move the .model lines outside the subcircuits. The way it is written now, you get two data structures per device, the instance (the device itself) and the model. The models can be shared, which should be faster.