OK - E/G sources are not possible (yet). But you can use b sources with pwl since release 20, e.g.:
Btest 1 0 I = pwl(v(1), -4,0, -2,2, 2,-2, 4,0)
Same for voltages.
DW
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I tried:
vin 1 0 dc 0 sin(0 3 50 0 0)
Btest 1 0 I = pwl(v(1), -4,0, -2,2, 2,-2, 4,0)
Rtest 1 0 1k
but with the precompiled version for windows I get:
******
** ngspice-20 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Please submit bug-reports to: ngspice-bugs@lists.sourceforge.net
** Creation Date: Nov 18 2009 00:07:28
******
Circuit: testschaltung lookup-table
PWL-INFO: prepare_PTF_PWL building a PTF_PWL
internal error -- segmentation violation
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
You are correct: there is something wrong with the windows binary - I will ask maintainer for that.
The following deck is working with the actual cvs version:
demonstrates usage of the pwl function in an ASRC
Vin 1 0 DC=0V
Btest 1 0 I = pwl(v(1), -4,-5, -2,0, 0,2, 2,0, 4,4)
.control
dc Vin -5 5 0.2
plot -Vin#branch vs v(1)
display all
.endc
.end
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
OK - E/G sources are not possible (yet). But you can use b sources with pwl since release 20, e.g.:
Btest 1 0 I = pwl(v(1), -4,0, -2,2, 2,-2, 4,0)
Same for voltages.
DW
Thanks for your comment.
But I can't understand: what is this pwl function inside the B source? I didnt find it in the ngspice manual and in http://newton.ex.ac.uk/teaching/CDHW/Electronics2/userguide/.
I tried:
vin 1 0 dc 0 sin(0 3 50 0 0)
Btest 1 0 I = pwl(v(1), -4,0, -2,2, 2,-2, 4,0)
Rtest 1 0 1k
but with the precompiled version for windows I get:
******
** ngspice-20 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Please submit bug-reports to: ngspice-bugs@lists.sourceforge.net
** Creation Date: Nov 18 2009 00:07:28
******
Circuit: testschaltung lookup-table
PWL-INFO: prepare_PTF_PWL building a PTF_PWL
internal error -- segmentation violation
You are correct: there is something wrong with the windows binary - I will ask maintainer for that.
The following deck is working with the actual cvs version:
demonstrates usage of the pwl function in an ASRC
Vin 1 0 DC=0V
Btest 1 0 I = pwl(v(1), -4,-5, -2,0, 0,2, 2,0, 4,4)
.control
dc Vin -5 5 0.2
plot -Vin#branch vs v(1)
display all
.endc
.end
Thanks for your help!
(I wait for the next release and will try again)
Mario
Is solved in cvs by using B sources and will be avaiable in win binary in file section.