I make an SR flip-flop, and ngspice.dll crash!

[fiveight]

Circuit Title
.tran 1ms 50s

aU1 [ S CP] NetU1_3 NAND
aU2 [ CP R] NetU2_3 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

aU3 [ NetU20_2 NetU1_3 NQ] Q NAND3
aU4 [ Q NetU2_3 NetU21_2] NQ NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

aU20 PR NetU20_2 NOT
aU21 CLR NetU21_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

.end

When S pin and R pin is 1, this SR flip-flop get into unstable state, and this make ngspice.dll to crash!

[fiveight]

Circuit Title
.tran 1ms 50s

aU1 [ Net1_1 NetC1_1] NetU1_3 NAND
aU2 [ NetC1_1 Net2_1] NetU2_3 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

aU3 [ NetU20_2 NetU1_3 Net6_1] Net5_1 NAND3
aU4 [ Net5_1 NetU2_3 NetU21_2] Net6_1 NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

aU20 Net3_1 NetU20_2 NOT
aU21 Net4_1 NetU21_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)

xC1 NetC1_1 CLOCK
.subckt CLOCK out  frequency = 200 dutycycle = 0.5 risedelay = 1e-6 falldelay = 1e-6
v1 1 0 DC 2
a1 1 out var_clock
.model var_clock d_osc(cntl_array = [-1.0 0.0 1.0 2.0] freq_array = [10 100 1e3 {frequency}] duty_cycle ={dutycycle} init_phase = 0 rise_delay = {risedelay} fall_delay = {falldelay})
.ends

x1 Net1_1 DCT
x2 Net2_1 DCT
x3 Net3_1 DCT
x4 Net4_1 DCT
.subckt DCT out 
v1 1 0 DC 5
v2 3 0 DC 2
r1 1 2 1k
abridge1 [2] [out] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s1 2 0 3 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends

x5 Net5_1 P
x6 Net6_1 P
.subckt P 1 
a1 1 2 InputBuffer
a2 2  Digload
.MODEL Digload d_pulldown(load = 1e-12)
.MODEL InputBuffer d_buffer (rise_delay = 1n fall_delay = 1n)
.ends

.end

[fiveight]

Sorry, I forgot post the simulating commands.
Use follow commands:

source 'c:\srflipflop.cir'
alter @v.x1.v2 = 0
alter @v.x2.v2 = 0
alter @v.x3.v2 = 2
alter @v.x4.v2 = 2
bg_run

[marcel hendrix]

Aha. With that the console version of ngspice starts in the illegal state
that you identified, and .OP (obviously) can not find the correct operation
point, making the run fail with "Transient solution failed -".

When I specify UIC to skip .OP, the tran starts and runs very slowly,
locking up windows 7 in quite a scary way by using an enormous amount
of diskspace, but ^C still is able to kill it.

Possibly the dll version does something it shouldn't in this case, but
I can't check that now.

-marcel

[Holger Vogt]

The problem is not if there is non-convergence.

The problem is that there are conditions that eat up all of the available memory (see my other post 5hrs ago).

This is not dll specific. It is a XSPICE bug, difficult to analyse. During tansient analysis, right at its beginning, function EVTiter(ckt) adds one event after the other with a timestep of 1e-9s, the given delay time. Each time step some memory is allocated. Changing the delay times to 1e-6s makes memory consumption a bit slower, but after 10% transient time 4GB are used up.

Basically this should not happen, illigal inputs to a logic device should cause U (unknown) at its output. Of course it is not a good idea to force an illigal condition right at the beginning of a simulation, but ngspice should then bail out gracefully.

Holger

[marcel hendrix]

Ok, the problem is not at t=0, but at t=5ms when CLK goes low and both
NAND1 and NAND2 go high. The two NAND3s then form a 2ns delay-line
oscillator. This generates a lot of output which NGSPICE stores in
memory when in interactive mode.

I modified the rise_delay and fall_delay of NAND3 and simulated
until 0.5ms after the oscillation started. The following statistics
were compiled:

tt=0.1ns CALLOCed memory: 181.1 MB, disk 41.2 MB
tt=1ns CALLOCed memory: 155.7 MB, disk 34.1 MB
tt=10ns CALLOCed memory: 40.7 MB, disk 4.5 MB
tt=100ns CALLOCed memory: 25.3 MB, disk 0.4 MB

For tt=1ns approximately 100MB/0.5ms = 0.2GB/ms is needed,
or 0.1 GB/ms when we take into account that CLK is low 50%
of the time. To simulate 150 ms, 15GB of main memory is
required. This will fail far before completion on a workstation
with 16GB memory (under Windows). I therefore doubt that
this circuit demonstrates a bug in XSPICE.

The attached circuit is not the one used for the statistics.
It contains analog monitor traces for all the digital nodes
as shown in srff_orig.png. Analog aliasing of the digital
traces could caused a wrong conclusion of U(ndefined)
signals.

-marcel

Circuit Title
* 6ms is enough (~8GB mem use!)
.tran 1ms 6ms uic  $ 50s

aU1 [ Net1_1 NetC1_1] NetU1_3 NAND
aU2 [ NetC1_1 Net2_1] NetU2_3 NAND
* input_load of 1mF ?
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-13)

aU3 [ NetU20_2 NetU1_3 Net6_1] Net5_1 NAND3
aU4 [ Net5_1 NetU2_3 NetU21_2] Net6_1 NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-13)

aU20 Net3_1 NetU20_2 NOT
aU21 Net4_1 NetU21_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-13)

xC1 NetC1_1 CLOCK
.subckt CLOCK out  frequency = 200 dutycycle = 0.5 risedelay = 1e-6 falldelay = 1e-6
v1 1 0 DC 2
a1 1 out var_clock
.model var_clock d_osc(cntl_array = [-1.0 0.0 1.0 2.0] freq_array = [10 100 1e3 {frequency}] duty_cycle ={dutycycle} init_phase = 0 rise_delay = {risedelay} fall_delay = {falldelay})
.ends

x1 Net1_1 DCT
x2 Net2_1 DCT
x3 Net3_1 DCT
x4 Net4_1 DCT
.subckt DCT out 
v1 1 0 DC 5
v2 3 0 DC 2
r1 1 2 1k
abridge1 [2] [out] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s1 2 0 3 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends

x5 Net5_1 P
x6 Net6_1 P
.subckt P 1 
a1 1 2 InputBuffer
a2 2  Digload
.MODEL Digload d_pulldown(load = 1e-12)
.MODEL InputBuffer d_buffer (rise_delay = 1n fall_delay = 1n)
.ends

* Analog monitor system
Autil [NetU1_3 NetU2_3 Net5_1 Net6_1 NetU20_2 NetU21_2 NetC1_1 Net1_1 Net2_1 Net3_1 Net4_1] [nand1 nand2 nand3_1 nand3_2 not1 not2 clk in1 in2 in3 in4] dac_buff
.model dac_buff dac_bridge(out_low=0 out_high=1 t_rise=10ns t_fall=10ns)

.control
  listing e
  alter @v.x1.v2 = 0
  alter @v.x2.v2 = 0
  alter @v.x3.v2 = 2
  alter @v.x4.v2 = 2
  run
  write srff_orig.raw
  quit
.endc

.end

[fiveight]

You can use this picture of my netlist.

[Holger Vogt]

Again this one does not crash ngspice.exe or ngspice.dll.

Holger

[Holger Vogt]

Fiveight,

the input file you have provided, does not crash ngspice (neither ngspice.exe nor ngspice.dll). It simply does not do anything, exept that the clock is toggling.

When you experience a crash with ngspice.dll, please test your input with standard ngspice.exe. If o.k. then, probably your interface to ngspice.dll has a problem. To solve this problem, your input to this mailing list is definitely not sufficient (see the questions below). When ngspice.exe crashes, we need to have an exact copy of the input file that leads to the crash. Of course you may simplify this file, but if then the crash is not there any more, we cannot help.

What ngspice version do you use?
What error messages do you experience?
How do you invoke the input file (ngspice.dll specific functions)?
What version of your input file crashes ngspice (please deliver exactly this one)?

Holger

[fiveight]

Sorry, I forgot post the simulating commands.
Use the spice I post second time and use follow commands:

source 'c:\srflipflop.cir'
alter @v.x1.v2 = 0
alter @v.x2.v2 = 0
alter @v.x3.v2 = 2
alter @v.x4.v2 = 2
bg_run

[Holger Vogt]

Things start becoming interesting:

By adding a control section

.control
*source 'c:\srflipflop.cir'
alter @v.x1.v2 = 0
alter @v.x2.v2 = 0
alter @v.x3.v2 = 2
alter @v.x4.v2 = 2
run
.endc

to your input file given above, I managed to stall my computer completely by calling standard ngspice.exe with

ngspice srflipflop.cir.

This is worth some further investigations!

Holger