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From: nasm-bot f. C. S. B. <cha...@in...> - 2018-05-05 20:48:24
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Commit-ID: 69ed82447a13a22e52a86a51a5657c7955a6767b Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=69ed82447a13a22e52a86a51a5657c7955a6767b Author: Chang S. Bae <cha...@in...> AuthorDate: Wed, 2 May 2018 08:07:51 -0700 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 5 May 2018 23:43:57 +0300 output: macho -- Check the actual size of 64-bit absolute address Even though the size is set to 64-bit, actual value can be in 32-bit range. In that case, the use of such absolute address is prevented. The side effect of 58d2ab17 is resolved. https://bugzilla.nasm.us/show_bug.cgi?id=3392468 Reported-by: Richard Russell <rtr...@gm...> Reported-by: Michael Petch <mp...@ca...> Signed-off-by: Chang S. Bae <cha...@in...> Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- output/outmacho.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/output/outmacho.c b/output/outmacho.c index 266a3dd..a92b9ec 100644 --- a/output/outmacho.c +++ b/output/outmacho.c @@ -670,7 +670,8 @@ static void macho_output(int32_t secto, const void *data, nasm_error(ERR_NONFATAL, "Mach-O format does not support" " section base references"); } else if (wrt == NO_SEG) { - if (fmt.ptrsize == 8 && asize != 8) { + if (fmt.ptrsize == 8 && + (asize != 8 || addr <= UINT32_MAX)) { nasm_error(ERR_NONFATAL, "Mach-O 64-bit format does not support" " 32-bit absolute addresses"); |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-04-20 08:46:48
|
Commit-ID: dfa70d8f146e2bb4b5e0405b774e57364b6091f9 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=dfa70d8f146e2bb4b5e0405b774e57364b6091f9 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 7 Apr 2018 12:50:25 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 7 Apr 2018 12:50:25 +0300 ci: First try Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- .travis.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.travis.yaml b/.travis.yaml new file mode 100644 index 0000000..46caee1 --- /dev/null +++ b/.travis.yaml @@ -0,0 +1,8 @@ +language: c +sudo: required +dist: trusty +cache: ccache +env: + - TR_ARCH=local +script: + - sudo make CCACHE=1 -C scripts/travis $TR_ARCH |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-26 18:17:46
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Commit-ID: fb9e00a1c3c3ec89d385175baa6e66b15318bda8 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=fb9e00a1c3c3ec89d385175baa6e66b15318bda8 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 25 Feb 2018 16:12:34 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 25 Feb 2018 16:12:34 +0300 output: outobj -- Fix typo in obj_init In 51b453b0970a1d66c3f6533ed940cb9838ba2b18 occasionally used wrong operand for sizeof. Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- output/outobj.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/output/outobj.c b/output/outobj.c index 054963b..bbf9015 100644 --- a/output/outobj.c +++ b/output/outobj.c @@ -640,7 +640,7 @@ static enum directive_result obj_directive(enum directive, char *, int); static void obj_init(void) { - strlcpy(obj_infile, inname, sizeof(inname)); + strlcpy(obj_infile, inname, sizeof(obj_infile)); first_seg = seg_alloc(); any_segs = false; fpubhead = NULL; |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-24 12:15:43
|
Commit-ID: fff27ab229c71b36e7d31a50ebae5088360332c8 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=fff27ab229c71b36e7d31a50ebae5088360332c8 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 24 Feb 2018 15:11:32 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 24 Feb 2018 15:11:32 +0300 compiler: Fix typo in 6686fc6 https://bugzilla.nasm.us/show_bug.cgi?id=3392464 Reported-by: se...@gm... Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- include/compiler.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/compiler.h b/include/compiler.h index aba773e..fb146af 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -296,7 +296,7 @@ size_t strnlen(const char *s, size_t maxlen); * This differs from unlikely() in that it is applied to a function call, * not a boolean condition. */ -#ifndef HAVE_FUNC_ATTRIBUTE_COLD +#ifdef HAVE_FUNC_ATTRIBUTE_COLD # define unlikely_func __attribute__((cold)) #else # define unlikely_func |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-09 21:42:30
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Commit-ID: 9f45a77f46829e666b35530939b9237cf978d4dc Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9f45a77f46829e666b35530939b9237cf978d4dc Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 10 Feb 2018 00:40:46 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 10 Feb 2018 00:40:46 +0300 nasmlib: Drop pure_func attrib from seg_alloc It not only reads static variable but writes it back as well. https://bugzilla.nasm.us/show_bug.cgi?id=3392461 Reported-by: Michael Šimáček <msi...@re...> Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- include/nasmlib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/nasmlib.h b/include/nasmlib.h index fee1b5e..69b81b7 100644 --- a/include/nasmlib.h +++ b/include/nasmlib.h @@ -190,7 +190,7 @@ int64_t readstrnum(char *str, int length, bool *warn); /* * seg_alloc: allocate a hitherto unused segment number. */ -int32_t pure_func seg_alloc(void); +int32_t seg_alloc(void); /* * many output formats will be able to make use of this: a standard |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-09 21:42:30
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Commit-ID: 5eb1838b4d3752fd863d19442943983a2a5ee87c Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=5eb1838b4d3752fd863d19442943983a2a5ee87c Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 10 Feb 2018 00:33:41 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 10 Feb 2018 00:34:10 +0300 nasmlib: Drop unused seg_init The helper has been eliminated in 2c4a4d5810d0a59b033a07876a2648ef5d4c2859 https://bugzilla.nasm.us/show_bug.cgi?id=3392461 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- include/nasmlib.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/nasmlib.h b/include/nasmlib.h index 79e866b..fee1b5e 100644 --- a/include/nasmlib.h +++ b/include/nasmlib.h @@ -188,10 +188,8 @@ int64_t readnum(char *str, bool *error); int64_t readstrnum(char *str, int length, bool *warn); /* - * seg_init: Initialise the segment-number allocator. * seg_alloc: allocate a hitherto unused segment number. */ -void pure_func seg_init(void); int32_t pure_func seg_alloc(void); /* |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-06 21:09:18
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Commit-ID: 7c640b757909d6d88242b4c2016d8121dddd2b48 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=7c640b757909d6d88242b4c2016d8121dddd2b48 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Wed, 7 Feb 2018 00:06:47 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Wed, 7 Feb 2018 00:06:47 +0300 NASM 2.13.03rc4 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index f409fd2..93e2879 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.13.03rc3 +2.13.03rc4 |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-06 20:09:23
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Commit-ID: 91f8aa7118f4c4386d142b3de165bed293dabb6b Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=91f8aa7118f4c4386d142b3de165bed293dabb6b Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Tue, 6 Feb 2018 23:04:58 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Tue, 6 Feb 2018 23:04:58 +0300 iflag: Fix iflag_cmp_cpu_level In commit a8f3698cf31a9379cf85416c6cb40c3340e90adb the iflag_cmp_cpu_level escaped updating. Fix it. Reported-by: Tomasz Kantecki <tom...@in...> Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- include/iflag.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/iflag.h b/include/iflag.h index 02787de..1cef9b6 100644 --- a/include/iflag.h +++ b/include/iflag.h @@ -131,9 +131,9 @@ static inline int iflag_cmp_cpu_level(const iflag_t *a, const iflag_t *b) iflag_clear(&v2, IF_CYRIX); iflag_clear(&v2, IF_AMD); - if (v1.field[3] < v2.field[3]) + if (v1.field[4] < v2.field[4]) return -1; - else if (v1.field[3] > v2.field[3]) + else if (v1.field[4] > v2.field[4]) return 1; return 0; |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-05 17:27:29
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Commit-ID: 4d7e680cb015e5d77764ff1cc83a417ecb73e31b Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=4d7e680cb015e5d77764ff1cc83a417ecb73e31b Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Mon, 5 Feb 2018 20:23:47 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Mon, 5 Feb 2018 20:23:47 +0300 NASM 2.13.03rc3 Need a new version due to occasional merge, see da1cb0e0003a9f2a6be141e4bc5273b1a8681b39 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index 2993c15..f409fd2 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.13.03rc2 +2.13.03rc3 |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-05 17:27:28
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Commit-ID: da1cb0e0003a9f2a6be141e4bc5273b1a8681b39 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=da1cb0e0003a9f2a6be141e4bc5273b1a8681b39 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Mon, 5 Feb 2018 20:20:48 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Mon, 5 Feb 2018 20:20:48 +0300 Revert "insns.dat: Add VAESENC, VAESENCLAST instructions" This reverts commit d625f85cd2a3abbdad610d222096a19368df09f9. Occasionally merged in from the master, while it was here already in different form. --- x86/insns.dat | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/x86/insns.dat b/x86/insns.dat index 0bc6d97..a05fdc7 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -5175,30 +5175,6 @@ PCOMMIT void [ 66 0f ae f8] ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD -;# Intel instruction extension based on pub number 319433-030 dated October 2017 - -; Intel VAES instructions -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE - -; Intel VAES + AVX512VL instructions -VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE - -; Intel VAES + AVX512F instructions -VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE -VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE -VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE -VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE - ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-05 17:18:18
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Commit-ID: 9254323fdf10fc00723566e653f6dee9058927fb Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9254323fdf10fc00723566e653f6dee9058927fb Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Mon, 5 Feb 2018 20:13:44 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Mon, 5 Feb 2018 20:13:44 +0300 changes.doc: document dwarf issue Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- doc/changes.src | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/changes.src b/doc/changes.src index 54a12e2..aad02a7 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -10,6 +10,7 @@ since 2007. \S{cl-2.13.03} Version 2.13.03 \b Added AVX and AVX512 \c{VAES*} and \c{VPCLMULQDQ} instructions. +\b Fixed missing dwarf record in x32 ELF output format. \S{cl-2.13.02} Version 2.13.02 |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-05 17:18:14
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Commit-ID: d287398b8df32b4593aad7cc7ea685433400cb9f Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=d287398b8df32b4593aad7cc7ea685433400cb9f Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Mon, 5 Feb 2018 20:14:25 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Mon, 5 Feb 2018 20:14:25 +0300 NASM 2.13.03rc2 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index 6ef13b1..2993c15 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.13.03rc1 +2.13.03rc2 |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-02-05 17:12:31
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Commit-ID: e0ff7b025ba5c4c469d72af9568c76c107ed0290 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=e0ff7b025ba5c4c469d72af9568c76c107ed0290 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 28 Jan 2018 00:56:18 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Mon, 5 Feb 2018 20:08:10 +0300 output: elf -- Add missing dwarf loc section Lost during elf engine unification in 4670887c4db772d2d44889fbc4509b3fb65b311f https://bugzilla.nasm.us/show_bug.cgi?id=3392459 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- output/outelf.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/output/outelf.c b/output/outelf.c index c1f949d..deac27f 100644 --- a/output/outelf.c +++ b/output/outelf.c @@ -3255,6 +3255,9 @@ static void dwarf_generate(void) if (is_elf32()) { WRITELONG(pbuf,0); /* null beginning offset */ WRITELONG(pbuf,0); /* null ending offset */ + } else if (is_elfx32()) { + WRITELONG(pbuf,0); /* null beginning offset */ + WRITELONG(pbuf,0); /* null ending offset */ } else { nasm_assert(is_elf64()); WRITEDLONG(pbuf,0); /* null beginning offset */ |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-01-27 21:57:31
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Commit-ID: 70c439b8de78595e9a465e3907aa282aa9c82984 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=70c439b8de78595e9a465e3907aa282aa9c82984 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 28 Jan 2018 00:56:18 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 28 Jan 2018 00:56:18 +0300 output: elf -- Add missing dwarf loc section Lost during elf engine unification in 4670887c4db772d2d44889fbc4509b3fb65b311f https://bugzilla.nasm.us/show_bug.cgi?id=3392459 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- output/outelf.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/output/outelf.c b/output/outelf.c index c0b37e4..4d04761 100644 --- a/output/outelf.c +++ b/output/outelf.c @@ -3274,6 +3274,9 @@ static void dwarf_generate(void) if (is_elf32()) { WRITELONG(pbuf,0); /* null beginning offset */ WRITELONG(pbuf,0); /* null ending offset */ + } else if (is_elfx32()) { + WRITELONG(pbuf,0); /* null beginning offset */ + WRITELONG(pbuf,0); /* null ending offset */ } else { nasm_assert(is_elf64()); WRITEDLONG(pbuf,0); /* null beginning offset */ |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-01-08 20:57:31
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Commit-ID: 7680602f868ad95b6f733abaeceb6e74bdab34b7 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=7680602f868ad95b6f733abaeceb6e74bdab34b7 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 17:17:19 +0300 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Mon, 8 Jan 2018 12:53:41 -0800 insns-flags: Add VPCLMULQDQ flag In sake of https://bugzilla.nasm.us/show_bug.cgi?id=3392455 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns-iflags.ph | 1 + 1 file changed, 1 insertion(+) diff --git a/x86/insns-iflags.ph b/x86/insns-iflags.ph index e1b7480..989276f 100644 --- a/x86/insns-iflags.ph +++ b/x86/insns-iflags.ph @@ -141,6 +141,7 @@ my %insns_flag_bit = ( "EVEX" => [ 95, "EVEX encoded instruction"], "AES" => [ 96, "AES instructions"], "VAES" => [ 97, "AES AVX instructions"], + "VPCLMULQDQ" => [ 98, "Carry-Less Multiplication extention"], # # dword bound, cpu type flags |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-01-08 20:57:30
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Commit-ID: 581fc6899b631e344339c478d9803e8a71c9670c Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=581fc6899b631e344339c478d9803e8a71c9670c Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 16:57:54 +0300 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Mon, 8 Jan 2018 12:53:32 -0800 insns.dat: Move VAES instructions to AES group Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns.dat | 49 +++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/x86/insns.dat b/x86/insns.dat index 8ceab04..f641382 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -2046,6 +2046,31 @@ VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDY VAESIMC xmmreg,xmmrm128 [rm: vex.128.66.0f38 db /r] AVX,SANDYBRIDGE VAESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE +;# Intel instruction extension based on pub number 319433-030 dated October 2017 + +; Intel VAES instructions +VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE +VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE +VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE +VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE + +; Intel VAES + AVX512VL instructions +VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE +VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE +VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE +VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE +VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE +VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE +VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE +VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE + +; Intel VAES + AVX512F instructions +VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE +VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE +VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE +VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE + + ;# Intel AVX instructions VADDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE VADDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE @@ -5123,30 +5148,6 @@ PCOMMIT void [ 66 0f ae f8] ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD -;# Intel instruction extension based on pub number 319433-030 dated October 2017 - -; Intel VAES instructions -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE - -; Intel VAES + AVX512VL instructions -VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE - -; Intel VAES + AVX512F instructions -VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE -VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE -VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE -VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE - ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC |
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From: nasm-bot f. C. G. <gor...@gm...> - 2018-01-08 20:57:28
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Commit-ID: a8f3698cf31a9379cf85416c6cb40c3340e90adb Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=a8f3698cf31a9379cf85416c6cb40c3340e90adb Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 16:46:10 +0300 Committer: H. Peter Anvin <hp...@zy...> CommitDate: Mon, 8 Jan 2018 12:53:19 -0800 insns-iflags: Add AES, VAES flags In sake of https://bugzilla.nasm.us/show_bug.cgi?id=3392454 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns-iflags.ph | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/x86/insns-iflags.ph b/x86/insns-iflags.ph index 84eda8f..e1b7480 100644 --- a/x86/insns-iflags.ph +++ b/x86/insns-iflags.ph @@ -139,31 +139,33 @@ my %insns_flag_bit = ( "OBSOLETE" => [ 93, "Instruction removed from architecture"], "VEX" => [ 94, "VEX or XOP encoded instruction"], "EVEX" => [ 95, "EVEX encoded instruction"], + "AES" => [ 96, "AES instructions"], + "VAES" => [ 97, "AES AVX instructions"], # - # dword bound, index 3 - cpu type flags + # dword bound, cpu type flags # # The CYRIX and AMD flags should have the highest bit values; the # disassembler selection algorithm depends on it. # - "8086" => [ 96, "8086"], - "186" => [ 97, "186+"], - "286" => [ 98, "286+"], - "386" => [ 99, "386+"], - "486" => [100, "486+"], - "PENT" => [101, "Pentium"], - "P6" => [102, "P6"], - "KATMAI" => [103, "Katmai"], - "WILLAMETTE" => [104, "Willamette"], - "PRESCOTT" => [105, "Prescott"], - "X86_64" => [106, "x86-64 (long or legacy mode)"], - "NEHALEM" => [107, "Nehalem"], - "WESTMERE" => [108, "Westmere"], - "SANDYBRIDGE" => [109, "Sandy Bridge"], - "FUTURE" => [110, "Future processor (not yet disclosed)"], - "IA64" => [111, "IA64 (in x86 mode)"], - "CYRIX" => [126, "Cyrix-specific"], - "AMD" => [127, "AMD-specific"], + "8086" => [128, "8086"], + "186" => [129, "186+"], + "286" => [130, "286+"], + "386" => [131, "386+"], + "486" => [132, "486+"], + "PENT" => [133, "Pentium"], + "P6" => [134, "P6"], + "KATMAI" => [135, "Katmai"], + "WILLAMETTE" => [136, "Willamette"], + "PRESCOTT" => [137, "Prescott"], + "X86_64" => [138, "x86-64 (long or legacy mode)"], + "NEHALEM" => [139, "Nehalem"], + "WESTMERE" => [140, "Westmere"], + "SANDYBRIDGE" => [141, "Sandy Bridge"], + "FUTURE" => [142, "Future processor (not yet disclosed)"], + "IA64" => [143, "IA64 (in x86 mode)"], + "CYRIX" => [144, "Cyrix-specific"], + "AMD" => [145, "AMD-specific"], ); my %insns_flag_hash = (); |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-12-29 14:24:41
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Commit-ID: f1f8ef48f4c946c79afc7ba53228e1b3dde1e2dd Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=f1f8ef48f4c946c79afc7ba53228e1b3dde1e2dd Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 17:17:19 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Fri, 29 Dec 2017 17:20:29 +0300 insns-flags: Add VPCLMULQDQ flag In sake of https://bugzilla.nasm.us/show_bug.cgi?id=3392455 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns-iflags.ph | 1 + 1 file changed, 1 insertion(+) diff --git a/x86/insns-iflags.ph b/x86/insns-iflags.ph index e1b7480..989276f 100644 --- a/x86/insns-iflags.ph +++ b/x86/insns-iflags.ph @@ -141,6 +141,7 @@ my %insns_flag_bit = ( "EVEX" => [ 95, "EVEX encoded instruction"], "AES" => [ 96, "AES instructions"], "VAES" => [ 97, "AES AVX instructions"], + "VPCLMULQDQ" => [ 98, "Carry-Less Multiplication extention"], # # dword bound, cpu type flags |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-12-29 14:24:40
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Commit-ID: 0ba95b776727c1b494995866d84c596a3cddb81e Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=0ba95b776727c1b494995866d84c596a3cddb81e Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 16:57:54 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Fri, 29 Dec 2017 17:20:25 +0300 insns.dat: Move VAES instructions to AES group Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns.dat | 49 +++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/x86/insns.dat b/x86/insns.dat index 072b4c4..7c65095 100644 --- a/x86/insns.dat +++ b/x86/insns.dat @@ -2048,6 +2048,31 @@ VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDY VAESIMC xmmreg,xmmrm128 [rm: vex.128.66.0f38 db /r] AVX,SANDYBRIDGE VAESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE +;# Intel instruction extension based on pub number 319433-030 dated October 2017 + +; Intel VAES instructions +VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE +VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE +VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE +VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE + +; Intel VAES + AVX512VL instructions +VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE +VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE +VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE +VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE +VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE +VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE +VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE +VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE + +; Intel VAES + AVX512F instructions +VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE +VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE +VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE +VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE + + ;# Intel AVX instructions VADDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE VADDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE @@ -5125,30 +5150,6 @@ PCOMMIT void [ 66 0f ae f8] ; AMD Zen v1 CLZERO void [ 0f 01 fc] FUTURE,AMD -;# Intel instruction extension based on pub number 319433-030 dated October 2017 - -; Intel VAES instructions -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE - -; Intel VAES + AVX512VL instructions -VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE -VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE - -; Intel VAES + AVX512F instructions -VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE -VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE -VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE -VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE - ;# Systematic names for the hinting nop instructions ; These should be last in the file HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-12-29 14:24:37
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Commit-ID: 73ab510c711a5f8a058179fe9d01ffc0f367f1e4 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=73ab510c711a5f8a058179fe9d01ffc0f367f1e4 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Fri, 29 Dec 2017 16:46:10 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Fri, 29 Dec 2017 17:20:17 +0300 insns-iflags: Add AES, VAES flags In sake of https://bugzilla.nasm.us/show_bug.cgi?id=3392454 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- x86/insns-iflags.ph | 40 +++++++++++++++++++++------------------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/x86/insns-iflags.ph b/x86/insns-iflags.ph index 84eda8f..e1b7480 100644 --- a/x86/insns-iflags.ph +++ b/x86/insns-iflags.ph @@ -139,31 +139,33 @@ my %insns_flag_bit = ( "OBSOLETE" => [ 93, "Instruction removed from architecture"], "VEX" => [ 94, "VEX or XOP encoded instruction"], "EVEX" => [ 95, "EVEX encoded instruction"], + "AES" => [ 96, "AES instructions"], + "VAES" => [ 97, "AES AVX instructions"], # - # dword bound, index 3 - cpu type flags + # dword bound, cpu type flags # # The CYRIX and AMD flags should have the highest bit values; the # disassembler selection algorithm depends on it. # - "8086" => [ 96, "8086"], - "186" => [ 97, "186+"], - "286" => [ 98, "286+"], - "386" => [ 99, "386+"], - "486" => [100, "486+"], - "PENT" => [101, "Pentium"], - "P6" => [102, "P6"], - "KATMAI" => [103, "Katmai"], - "WILLAMETTE" => [104, "Willamette"], - "PRESCOTT" => [105, "Prescott"], - "X86_64" => [106, "x86-64 (long or legacy mode)"], - "NEHALEM" => [107, "Nehalem"], - "WESTMERE" => [108, "Westmere"], - "SANDYBRIDGE" => [109, "Sandy Bridge"], - "FUTURE" => [110, "Future processor (not yet disclosed)"], - "IA64" => [111, "IA64 (in x86 mode)"], - "CYRIX" => [126, "Cyrix-specific"], - "AMD" => [127, "AMD-specific"], + "8086" => [128, "8086"], + "186" => [129, "186+"], + "286" => [130, "286+"], + "386" => [131, "386+"], + "486" => [132, "486+"], + "PENT" => [133, "Pentium"], + "P6" => [134, "P6"], + "KATMAI" => [135, "Katmai"], + "WILLAMETTE" => [136, "Willamette"], + "PRESCOTT" => [137, "Prescott"], + "X86_64" => [138, "x86-64 (long or legacy mode)"], + "NEHALEM" => [139, "Nehalem"], + "WESTMERE" => [140, "Westmere"], + "SANDYBRIDGE" => [141, "Sandy Bridge"], + "FUTURE" => [142, "Future processor (not yet disclosed)"], + "IA64" => [143, "IA64 (in x86 mode)"], + "CYRIX" => [144, "Cyrix-specific"], + "AMD" => [145, "AMD-specific"], ); my %insns_flag_hash = (); |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-11-25 21:42:28
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Commit-ID: d44a7c0a7caa75df19fabe78974a1161e2a7a7e5 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=d44a7c0a7caa75df19fabe78974a1161e2a7a7e5 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 26 Nov 2017 00:36:22 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 26 Nov 2017 00:36:49 +0300 NASM 2.13.02rc3 --- version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/version b/version index c7285b3..b5e3e8e 100644 --- a/version +++ b/version @@ -1 +1 @@ -2.13.02rc2 +2.13.02rc3 |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-11-25 14:44:13
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Commit-ID: 8e2307caca9600d5b9a033b5d898d4dea81181d6 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=8e2307caca9600d5b9a033b5d898d4dea81181d6 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 25 Nov 2017 17:42:45 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 25 Nov 2017 17:42:45 +0300 docs: changes -- Drop leftover Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- doc/changes.src | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/changes.src b/doc/changes.src index 9a5005d..5f1ece3 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -25,7 +25,7 @@ since 2007. \b Fix false positive in testing of numeric overflows. -\b Fix generation of \c{PEXTRW} instruction for. +\b Fix generation of \c{PEXTRW} instruction. \b Fix \c{smartalign} package which can trigger an error during compiling if alignment code grows too big. |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-11-25 14:42:30
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Commit-ID: 4c171ce268bb5d091ff49eb40d9709bef6e0a8dd Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=4c171ce268bb5d091ff49eb40d9709bef6e0a8dd Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sat, 25 Nov 2017 17:41:38 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sat, 25 Nov 2017 17:41:38 +0300 doc: Update changes for 2.13.02 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- doc/changes.src | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/doc/changes.src b/doc/changes.src index 09d68df..9a5005d 100644 --- a/doc/changes.src +++ b/doc/changes.src @@ -9,6 +9,42 @@ since 2007. \S{cl-2.13.02} Version 2.13.02 +\b Fix buffer overflow in specially malformed preprocessor + token directive. + +\b Fix null dereference in case if data missed with implicit + pasting preprocessor mode. + +\b Fix null dereference in conditional preprocessing. + +\b Fix null dereference in malformed multiline and singleline + macros arguments. + +\b Fix accessing of arbitrary memory on unterminated strings in + prepocessor mode. + +\b Fix false positive in testing of numeric overflows. + +\b Fix generation of \c{PEXTRW} instruction for. + +\b Fix \c{smartalign} package which can trigger an error during + compiling if alignment code grows too big. + +\b Fix a case where negative value in \c{TIMES} directive causes + panic while error should be printed instead. + +\b Always finalize \c{.debug_abbrev} section with a null in + \c{dwarf} output format. + +\b Support \c{debug} flag in section attributes for \c{macho} + output format. + +\b Support up to 16 characters in section names for \c{macho} + output format. + +\b Fix missing update of global \c{BITS} setting if \c{SECTION} + directive requested to. + \b Fix the incorrect generation of VEX-encoded instruction when static mode decorators are specified on scalar instructions, losing the decorators as they require EVEX encoding. |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-10-22 18:44:13
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Commit-ID: 9b7ee09abfd426b99aa1ea81d19a3b2818eeabf9 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=9b7ee09abfd426b99aa1ea81d19a3b2818eeabf9 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 22 Oct 2017 21:42:59 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 22 Oct 2017 21:42:59 +0300 prepoc: Fix heap-buffer-overflow in detoken Just make sure we've a data to process. https://bugzilla.nasm.us/show_bug.cgi?id=3392424 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- asm/preproc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/asm/preproc.c b/asm/preproc.c index 9642edc..475926d 100644 --- a/asm/preproc.c +++ b/asm/preproc.c @@ -1254,7 +1254,8 @@ static char *detoken(Token * tlist, bool expand_locals) int len = 0; list_for_each(t, tlist) { - if (t->type == TOK_PREPROC_ID && t->text[1] == '!') { + if (t->type == TOK_PREPROC_ID && t->text && + t->text[0] && t->text[1] == '!') { char *v; char *q = t->text; |
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From: nasm-bot f. C. G. <gor...@gm...> - 2017-10-22 18:30:42
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Commit-ID: 6f8109ebf18e3de69a8a2ad63867fe8498e49bf0 Gitweb: http://repo.or.cz/w/nasm.git?a=commitdiff;h=6f8109ebf18e3de69a8a2ad63867fe8498e49bf0 Author: Cyrill Gorcunov <gor...@gm...> AuthorDate: Sun, 22 Oct 2017 21:26:36 +0300 Committer: Cyrill Gorcunov <gor...@gm...> CommitDate: Sun, 22 Oct 2017 21:26:36 +0300 preproc: Fix SIGSEGV if not data provided for implicit pasting https://bugzilla.nasm.us/show_bug.cgi?id=3392423 Signed-off-by: Cyrill Gorcunov <gor...@gm...> --- asm/preproc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/asm/preproc.c b/asm/preproc.c index 43b62aa..9642edc 100644 --- a/asm/preproc.c +++ b/asm/preproc.c @@ -3848,8 +3848,8 @@ static bool paste_tokens(Token **head, const struct tokseq_match *m, next = next->next; } - /* No match */ - if (tok == next) + /* No match or no text to process */ + if (tok == next || len == 0) break; len += strlen(tok->text); |
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