nasm-cvs — CVS commit messages

[nasm:master] Add IF_TBM flag

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  579f161d4817b69c701a2dbb48995207bda8fd41
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=579f161d4817b69c701a2dbb48995207bda8fd41
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Fri, 10 May 2013 13:24:15 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Fri, 10 May 2013 13:24:15 +0400

Add IF_TBM flag

For TMB instructions

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/insns.h b/insns.h
index 5ab58fa..d258910 100644
--- a/insns.h
+++ b/insns.h
@@ -118,6 +118,7 @@ extern const uint8_t nasm_bytecodes[];
 #define IF_FMA          0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_BMI1         0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_BMI2         0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
+#define IF_TBM          0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_HLE          0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_RTM          0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */
 #define IF_INVPCID      0x00000000UL    /* HACK NEED TO REORGANIZE THESE BITS */

[nasm:master] BR3392253: Fix potential buffer overflow in number conversion

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  ce6527459f0144a57fc628e0c978594daf1db281
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=ce6527459f0144a57fc628e0c978594daf1db281
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Mon, 6 May 2013 23:43:43 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 6 May 2013 23:43:43 +0400

BR3392253: Fix potential buffer overflow in number conversion

Reported-by: fra...@es...
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 preproc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/preproc.c b/preproc.c
index 8984a52..e2b12e4 100644
--- a/preproc.c
+++ b/preproc.c
@@ -5206,7 +5206,7 @@ static void pp_extra_stdmac(macros_t *macros)
 
 static void make_tok_num(Token * tok, int64_t val)
 {
-    char numbuf[20];
+    char numbuf[32];
     snprintf(numbuf, sizeof(numbuf), "%"PRId64"", val);
     tok->text = nasm_strdup(numbuf);
     tok->type = TOK_NUMBER;

[nasm:master] br3392250: insns -- Allow byte size in PREFETCHTx instructions

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  e3574117ed465f0a63c17c8703a731ac4fa6e6ca
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=e3574117ed465f0a63c17c8703a731ac4fa6e6ca
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 4 May 2013 02:24:05 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 4 May 2013 02:24:05 +0400

br3392250: insns -- Allow byte size in PREFETCHTx instructions

The PREFETCHTx instructions do allow mem8 (byte).

Reported-by: Agner <ag...@ag...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.dat | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/insns.dat b/insns.dat
index 99b0404..d5d7b93 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1588,10 +1588,10 @@ XRSTOR64	mem				[m:	o64 np 0f ae /5]			LONG,NEHALEM
 ; These instructions are not SSE-specific; they are
 ;# Generic memory operations
 ; and work even if CR4.OSFXFR == 0
-PREFETCHNTA	mem				[m:	0f 18 /0]				KATMAI
-PREFETCHT0	mem				[m:	0f 18 /1]				KATMAI
-PREFETCHT1	mem				[m:	0f 18 /2]				KATMAI
-PREFETCHT2	mem				[m:	0f 18 /3]				KATMAI
+PREFETCHNTA	mem8				[m:	0f 18 /0]				KATMAI
+PREFETCHT0	mem8				[m:	0f 18 /1]				KATMAI
+PREFETCHT1	mem8				[m:	0f 18 /2]				KATMAI
+PREFETCHT2	mem8				[m:	0f 18 /3]				KATMAI
 SFENCE		void				[	np 0f ae f8]				KATMAI
 
 ;# New MMX instructions introduced in Katmai

[nasm:master] insns.dat: Udate year

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  1ac3459539fd8d499e23d1c776dfe2642c1c331f
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=1ac3459539fd8d499e23d1c776dfe2642c1c331f
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 4 May 2013 02:24:38 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 4 May 2013 02:24:38 +0400

insns.dat: Udate year

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.dat | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/insns.dat b/insns.dat
index d5d7b93..f962221 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1,6 +1,6 @@
 ;; --------------------------------------------------------------------------
 ;;
-;;   Copyright 1996-2012 The NASM Authors - All Rights Reserved
+;;   Copyright 1996-2013 The NASM Authors - All Rights Reserved
 ;;   See the file AUTHORS included with the NASM distribution for
 ;;   the specific copyright holders.
 ;;

[nasm:master] BR3392244: docs -- Fix "respectively" typo

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  f47001175183b1ac3746e7832608cbc5077dfa65
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=f47001175183b1ac3746e7832608cbc5077dfa65
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sun, 28 Apr 2013 15:07:38 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sun, 28 Apr 2013 15:07:38 +0400

BR3392244: docs -- Fix "respectively" typo

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 doc/nasmdoc.src | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/doc/nasmdoc.src b/doc/nasmdoc.src
index 55dbfc0..8386eac 100644
--- a/doc/nasmdoc.src
+++ b/doc/nasmdoc.src
@@ -7631,7 +7631,7 @@ set to zero.
 \H{reg64} Register Names in 64-bit Mode
 
 NASM uses the following names for general-purpose registers in 64-bit
-mode, for 8-, 16-, 32- and 64-bit references, respecitively:
+mode, for 8-, 16-, 32- and 64-bit references, respectively:
 
 \c      AL/AH, CL/CH, DL/DH, BL/BH, SPL, BPL, SIL, DIL, R8B-R15B
 \c      AX, CX, DX, BX, SP, BP, SI, DI, R8W-R15W

[nasm:master] BR3392248: Update nasm -h output

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  deb082d63384de5810e7dfe2b7e63e67c3e2cce1
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=deb082d63384de5810e7dfe2b7e63e67c3e2cce1
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:37:17 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:37:17 +0400

BR3392248: Update nasm -h output

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 nasm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/nasm.c b/nasm.c
index 4896d70..126f271 100644
--- a/nasm.c
+++ b/nasm.c
@@ -784,6 +784,9 @@ static bool process_arg(char *p, char *q)
                  "    -Z<file>    redirect error messages to file\n"
                  "    -s          redirect error messages to stdout\n\n"
                  "    -F format   select a debugging format\n\n"
+                 "    -o outfile  write output to an outfile\n\n"
+                 "    -f format   select an output format\n\n"
+                 "    -l listfile write listing to a listfile\n\n"
                  "    -I<path>    adds a pathname to the include file path\n");
             printf
                 ("    -O<digit>   optimize branch offsets\n"
@@ -796,6 +799,7 @@ static bool process_arg(char *p, char *q)
                  "    -X<format>  specifies error reporting format (gnu or vc)\n"
                  "    -w+foo      enables warning foo (equiv. -Wfoo)\n"
                  "    -w-foo      disable warning foo (equiv. -Wno-foo)\n\n"
+                 "    -h          show invocation summary and exit\n\n"
                  "--prefix,--postfix\n"
                  "  this options prepend or append the given argument to all\n"
                  "  extern and global variables\n\n"

[nasm:master] BR3392248: Update ndisasm man

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  4de8f4efb7211a36fc8dc572289009d2506e529c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=4de8f4efb7211a36fc8dc572289009d2506e529c
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:13:51 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:13:51 +0400

BR3392248: Update ndisasm man

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 ndisasm.txt | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/ndisasm.txt b/ndisasm.txt
index a5f1e59..3fc382a 100644
--- a/ndisasm.txt
+++ b/ndisasm.txt
@@ -21,54 +21,54 @@ infile and directs it to stdout.
 
 OPTIONS
 -------
--h::
+*-h*::
 	Causes *ndisasm* to exit immediately, after giving a summary
 	of its invocation options.
 
--r::
+*-r*::
 	Causes *ndisasm* to exit immediately, after displaying its
 	version number.
 
--o 'origin'::
+*-o* 'origin'::
 	Specifies the notional load address for the file. This
 	option causes *ndisasm* to get the addresses it lists
 	down the left hand margin, and the target addresses
 	of PC-relative jumps and calls, right.
 
--s 'sync-point'::
+*-s* 'sync-point'::
 	Manually specifies a synchronisation address, such that
 	*ndisasm* will not output any machine instruction which
 	encompasses bytes on both sides of the address. Hence
 	the instruction which starts at that address will be
 	correctly disassembled.
 
--e 'hdrlen'::
+*-e* 'hdrlen'::
 	Specifies a number of bytes to discard from the beginning
 	of the file before starting disassembly. This does not
 	count towards the calculation of the disassembly offset:
 	the first 'disassembled' instruction will be shown starting
 	at the given load address.
 
--k 'offset,length'::
+*-k* 'offset,length'::
 	Specifies that 'length' bytes, starting from disassembly
 	offset 'offset', should be skipped over without generating
 	any output. The skipped bytes still count towards the
 	calculation of the disassembly offset.
 
--a|-i::
+*-a*|*-i*::
 	Enables automatic (or intelligent) sync mode, in which
 	*ndisasm* will attempt to guess where synchronisation should
 	be performed, by means of examining the target addresses
 	of the relative jumps and calls it disassembles.
 
--b 'bits'::
+*-b* 'bits'::
 	Specifies 16-, 32- or 64-bit mode. The default is 16-bit
 	mode.
 
--u::
+*-u*::
 	Specifies 32-bit mode, more compactly than using `-b 32'.
 
--p 'vendor'::
+*-p* 'vendor'::
 	Prefers instructions as defined by 'vendor' in case of
 	a conflict. Known 'vendor' names include *intel*, *amd*,
 	*cyrix*, and *idt*. The default is *intel*.

[nasm:master] BR3392248: Update nasm manual

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  895139cbd54463da0310c6ddb9e708925bfb374c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=895139cbd54463da0310c6ddb9e708925bfb374c
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:24:01 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:24:01 +0400

BR3392248: Update nasm manual

Add -W description

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 nasm.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/nasm.txt b/nasm.txt
index c6f5681..55f9a05 100644
--- a/nasm.txt
+++ b/nasm.txt
@@ -121,6 +121,10 @@ OPTIONS
 *-v*::
 	Causes *nasm* to exit immediately, after displaying its version number.
 
+*-W[no-]foo'::
+	Causes *nasm* to enable or disable certain classes of warning messages,
+	in gcc-like style, for example *-Worphan-labels* or *-Wno-orphan-labels*.
+
 *-w*'[+-]foo'::
 	Causes *nasm* to enable or disable certain classes of warning messages,
 	for example *-w+orphan-labels* or *-w-macro-params*.

[nasm:master] ndisasm: man -- Add missing -p option

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  567cc681a4e2fbceb26f8e0b54112bb2198b5292
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=567cc681a4e2fbceb26f8e0b54112bb2198b5292
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:18:46 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:18:46 +0400

ndisasm: man -- Add missing -p option

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 ndisasm.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ndisasm.txt b/ndisasm.txt
index 7e6105b..eaccfe4 100644
--- a/ndisasm.txt
+++ b/ndisasm.txt
@@ -11,7 +11,7 @@ ndisasm - the Netwide Disassembler, an 80x86 binary file disassembler
 SYNOPSIS
 --------
 *ndisasm* [ *-o* origin ] [ *-s* sync-point [...]] [ *-a* | *-i* ]
-	[ *-b* bits ] [ *-u* ] [ *-e* hdrlen ]
+	[ *-b* bits ] [ *-u* ] [ *-e* hdrlen ] [ *-p* vendor ]
 	[ *-k* offset,length [...]] infile
 
 DESCRIPTION

[nasm:master] BR3392248: Update ndisasm man

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  24543963b462ccfb42b71506baf64929b84f1e31
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=24543963b462ccfb42b71506baf64929b84f1e31
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:14:45 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:14:45 +0400

BR3392248: Update ndisasm man

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 ndisasm.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ndisasm.txt b/ndisasm.txt
index 3fc382a..7e6105b 100644
--- a/ndisasm.txt
+++ b/ndisasm.txt
@@ -25,7 +25,7 @@ OPTIONS
 	Causes *ndisasm* to exit immediately, after giving a summary
 	of its invocation options.
 
-*-r*::
+*-r*|*-v*::
 	Causes *ndisasm* to exit immediately, after displaying its
 	version number.
 

[nasm:master] BR3392248: Update nasm manual

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  9563d09da6d68194ad1b410048c170b3a6a4f494
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=9563d09da6d68194ad1b410048c170b3a6a4f494
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 20 Apr 2013 20:10:15 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 20 Apr 2013 20:10:15 +0400

BR3392248: Update nasm manual

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 nasm.txt | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/nasm.txt b/nasm.txt
index dde95ba..c6f5681 100644
--- a/nasm.txt
+++ b/nasm.txt
@@ -33,7 +33,7 @@ OPTIONS
 *-D*|*-d* 'macro[=value]'::
 	Pre-defines a single-line macro.
 
-*-e*::
+*-E*|*-e*::
 	Causes *nasm* to preprocess the given input file, and write the output to
 	'stdout' (or the specified output file name), and not actually assemble
 	anything.
@@ -42,8 +42,12 @@ OPTIONS
 	Specifies the output file format. To see a list of valid output formats,
 	use the *-hf* option.
 
+*-F* 'format'::
+	Specifies the debug information format. To see a list of valid output
+	formats, use the *-y* option (for example *-felf -y*).
+
 *-g*::
-	Causes *nasm* to generate debug information in selected format
+	Causes *nasm* to generate debug information in selected format.
 
 *-h*::
 	Causes *nasm* to exit immediately, after giving a summary of its
@@ -124,6 +128,9 @@ OPTIONS
 *-X* 'format'::
 	Specifies error reporting format (gnu or vc).
 
+*-y*::
+	Causes *nasm* to list supported debug formats.
+
 *-Z* 'filename'::
 	Causes *nasm* to redirect error messages to 'filename'. This option exists
 	to support operating systems on which stderr is not easily redirected.

[nasm:master] Fixed several resource and memory leaks

[nasm-bot f. P. K. <phi...@we...>]

Commit-ID:  dae212d049b1c6f737f14fe5c904adb6da432d8c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=dae212d049b1c6f737f14fe5c904adb6da432d8c
Author:     Philipp Kloke <phi...@we...>
AuthorDate: Sun, 31 Mar 2013 12:02:30 +0200
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 1 Apr 2013 02:16:27 +0400

Fixed several resource and memory leaks

Bug found by: CppCheck 1.59 (static source analysis tool)

Signed-off-by: Philipp Kloke <phi...@we...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c      | 1 +
 rdoff/ldrdf.c   | 2 ++
 rdoff/rdfload.c | 1 +
 rdoff/rdlib.c   | 3 ++-
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/assemble.c b/assemble.c
index 235be13..b119f86 100644
--- a/assemble.c
+++ b/assemble.c
@@ -424,6 +424,7 @@ int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
         } else if (fseek(fp, 0L, SEEK_END) < 0) {
             error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
                   fname);
+            fclose(fp);
         } else {
             static char buf[4096];
             size_t t = instruction->times;
diff --git a/rdoff/ldrdf.c b/rdoff/ldrdf.c
index 2ddada3..7c61d4c 100644
--- a/rdoff/ldrdf.c
+++ b/rdoff/ldrdf.c
@@ -1275,12 +1275,14 @@ int main(int argc, char **argv)
                     if ((p = strchr(buf, '\n')) != NULL)
                         *p = '\0';
                     if (i >= 128) {
+                        fclose(f);
                         fprintf(stderr, "ldrdf: too many input files\n");
                         exit(1);
                     }
                     *(respstrings + i) = newstr(buf);
                     argc++, i++;
                 }
+                fclose(f);
                 break;
             }
         case '2':
diff --git a/rdoff/rdfload.c b/rdoff/rdfload.c
index 4fd3dbd..5a7ab63 100644
--- a/rdoff/rdfload.c
+++ b/rdoff/rdfload.c
@@ -94,6 +94,7 @@ rdfmodule *rdfload(const char *filename)
         if (f->d)
             free(f->d);
         free(f);
+        free(hdr);
         return NULL;
     }
 
diff --git a/rdoff/rdlib.c b/rdoff/rdlib.c
index 31dbdb4..838f140 100644
--- a/rdoff/rdlib.c
+++ b/rdoff/rdlib.c
@@ -59,7 +59,7 @@ char *rdl_errors[5] = {
 
 int rdl_verify(const char *filename)
 {
-    FILE *fp = fopen(filename, "rb");
+    FILE *fp;
     char buf[257];
     int i;
     int32_t length;
@@ -69,6 +69,7 @@ int rdl_verify(const char *filename)
     if (lastresult != -1 && !strcmp(filename, lastverified))
         return lastresult;
 
+    fp = fopen(filename, "rb");
     strcpy(lastverified, filename);
 
     if (!fp)

[nasm:master] Fixed three possible buffer overflows

[nasm-bot f. P. K. <phi...@we...>]

Commit-ID:  efe66c65d183417cfc5a8ea6ae344b69fa29d897
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=efe66c65d183417cfc5a8ea6ae344b69fa29d897
Author:     Philipp Kloke <phi...@we...>
AuthorDate: Sun, 31 Mar 2013 12:03:47 +0200
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 1 Apr 2013 02:16:58 +0400

Fixed three possible buffer overflows

Bug found by: CppCheck 1.59 (static source analysis tool)

Signed-off-by: Philipp Kloke <phi...@we...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 rdoff/rdlib.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/rdoff/rdlib.c b/rdoff/rdlib.c
index 838f140..038b6fc 100644
--- a/rdoff/rdlib.c
+++ b/rdoff/rdlib.c
@@ -78,7 +78,7 @@ int rdl_verify(const char *filename)
     while (!feof(fp)) {
         i = 0;
 
-        while (fread(buf + i, 1, 1, fp) == 1 && buf[i] && i < 257)
+        while (fread(buf + i, 1, 1, fp) == 1 && i < 257 && buf[i])
             i++;
         if (feof(fp))
             break;
@@ -162,7 +162,7 @@ int rdl_searchlib(struct librarynode *lib, const char *label, rdffile * f)
         i = strlen(lib->name);
         buf[i++] = '.';
         t = i;
-        while (fread(buf + i, 1, 1, lib->fp) == 1 && buf[i] && i < 512)
+        while (fread(buf + i, 1, 1, lib->fp) == 1 && i < 512 && buf[i])
             i++;
 
         buf[i] = 0;
@@ -239,7 +239,7 @@ int rdl_openmodule(struct librarynode *lib, int moduleno, rdffile * f)
         i = strlen(buf);
         buf[i++] = '.';
         t = i;
-        while (fread(buf + i, 1, 1, lib->fp) == 1 && buf[i] && i < 512)
+        while (fread(buf + i, 1, 1, lib->fp) == 1 && i < 512 && buf[i])
             i++;
         buf[i] = 0;
         if (feof(lib->fp))

[nasm:master] Fixed wrong format specifier in format string

[nasm-bot f. P. K. <phi...@we...>]

Commit-ID:  91a2f99346212684c2c87df835fc0791dcc9ad96
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=91a2f99346212684c2c87df835fc0791dcc9ad96
Author:     Philipp Kloke <phi...@we...>
AuthorDate: Sun, 31 Mar 2013 12:00:09 +0200
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 1 Apr 2013 02:11:51 +0400

Fixed wrong format specifier in format string

Signed-off-by: Philipp Kloke <phi...@we...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 output/outdbg.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/output/outdbg.c b/output/outdbg.c
index 675af83..2b75039 100644
--- a/output/outdbg.c
+++ b/output/outdbg.c
@@ -172,8 +172,8 @@ static void dbg_out(int32_t segto, const void *data,
 
 static void dbg_sectalign(int32_t seg, unsigned int value)
 {
-    fprintf(ofile, "set alignment (%d) for segment (%d)\n",
-            seg, value);	
+    fprintf(ofile, "set alignment (%d) for segment (%u)\n",
+            seg, value);
 }
 
 static int32_t dbg_segbase(int32_t segment)

[nasm:master] Remove unnecessary calls to memset

[nasm-bot f. P. K. <phi...@we...>]

Commit-ID:  c51a224ceb9ebdc8ee4477a92d79f070918abf36
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=c51a224ceb9ebdc8ee4477a92d79f070918abf36
Author:     Philipp Kloke <phi...@we...>
AuthorDate: Sun, 31 Mar 2013 11:59:22 +0200
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 1 Apr 2013 02:11:01 +0400

Remove unnecessary calls to memset

The C standard guarantees that strncpy pads
the string with zeros if source string is smaller
than destination buffer.

Signed-off-by: Philipp Kloke <phi...@we...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 output/outcoff.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/output/outcoff.c b/output/outcoff.c
index 6c72806..258363f 100644
--- a/output/outcoff.c
+++ b/output/outcoff.c
@@ -945,7 +945,6 @@ static void coff_section_header(char *name, int32_t vsize,
 
     (void)vsize;
 
-    memset(padname, 0, 8);
     strncpy(padname, name, 8);
     fwrite(padname, 8, 1, ofile);
 
@@ -998,7 +997,6 @@ static void coff_symbol(char *name, int32_t strpos, int32_t value,
     char padname[8];
 
     if (name) {
-        memset(padname, 0, 8);
         strncpy(padname, name, 8);
         fwrite(padname, 8, 1, ofile);
     } else {
@@ -1023,7 +1021,6 @@ static void coff_write_symbols(void)
      * The `.file' record, and the file name auxiliary record.
      */
     coff_symbol(".file", 0L, 0L, -2, 0, 0x67, 1);
-    memset(filename, 0, 18);
     strncpy(filename, coff_infile, 18);
     fwrite(filename, 18, 1, ofile);
 

[nasm:master] Fixed wrong/redundant comparison according to documentation in comment above.

[nasm-bot f. P. K. <phi...@we...>]

Commit-ID:  b432f5774123e20a210c473a85c102333514d1f1
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=b432f5774123e20a210c473a85c102333514d1f1
Author:     Philipp Kloke <phi...@we...>
AuthorDate: Sun, 31 Mar 2013 12:01:23 +0200
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 1 Apr 2013 02:13:41 +0400

Fixed wrong/redundant comparison according to documentation in comment above.

Bug found by: CppCheck 1.59 (static source analysis tool)

Signed-off-by: Philipp Kloke <phi...@we...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 preproc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/preproc.c b/preproc.c
index 0ca360e..8984a52 100644
--- a/preproc.c
+++ b/preproc.c
@@ -2175,7 +2175,7 @@ static int do_directive(Token * tline)
      * since they are known to be buggy at moment, we need to fix them
      * in future release (2.09-2.10)
      */
-    if (i == PP_RMACRO || i == PP_RMACRO || i == PP_EXITMACRO) {
+    if (i == PP_RMACRO || i == PP_IRMACRO || i == PP_EXITMACRO) {
         error(ERR_NONFATAL, "unknown preprocessor directive `%s'",
               tline->text);
        return NO_DIRECTIVE_FOUND;

[nasm:master] Make F2 and F3 SSE prefixes override 66

[nasm-bot f. B. Rudiak-G. <ben...@gm...>]

Commit-ID:  94ba02fa16593ac1c6f0a99edce551b79f66e03b
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=94ba02fa16593ac1c6f0a99edce551b79f66e03b
Author:     Ben Rudiak-Gould <ben...@gm...>
AuthorDate: Sun, 10 Mar 2013 21:46:12 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sun, 10 Mar 2013 21:46:12 +0400

Make F2 and F3 SSE prefixes override 66

According to XED and experimentation, the 66 is ignored.

Signed-off-by: Ben Rudiak-Gould <ben...@gm...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 11 +----------
 disasm.c   | 12 ------------
 insns.pl   |  4 ++--
 3 files changed, 3 insertions(+), 24 deletions(-)

diff --git a/assemble.c b/assemble.c
index be3caaf..235be13 100644
--- a/assemble.c
+++ b/assemble.c
@@ -126,8 +126,6 @@
  * \341          - this instruction needs a WAIT "prefix"
  * \360          - no SSE prefix (== \364\331)
  * \361          - 66 SSE prefix (== \366\331)
- * \362          - F2 SSE prefix (== \364\332)
- * \363          - F3 SSE prefix (== \364\333)
  * \364          - operand-size prefix (0x66) not permitted
  * \365          - address-size prefix (0x67) not permitted
  * \366          - operand-size prefix (0x66) used as opcode extension
@@ -1049,7 +1047,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
         case 0360:
             break;
 
-        case3(0361):
+        case 0361:
             length++;
             break;
 
@@ -1603,13 +1601,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
             offset += 1;
             break;
 
-        case 0362:
-        case 0363:
-            bytes[0] = c - 0362 + 0xf2;
-            out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
-            offset += 1;
-            break;
-
         case 0364:
         case 0365:
             break;
diff --git a/disasm.c b/disasm.c
index 89e16ab..97bf27e 100644
--- a/disasm.c
+++ b/disasm.c
@@ -834,18 +834,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
 	    o_used = true;
 	    break;
 
-	case 0362:
-	    if (prefix->osp || prefix->rep != 0xf2)
-		return false;
-	    drep = 0;
-	    break;
-
-	case 0363:
-	    if (prefix->osp || prefix->rep != 0xf3)
-		return false;
-	    drep = 0;
-	    break;
-
 	case 0364:
 	    if (prefix->osp)
 		return false;
diff --git a/insns.pl b/insns.pl
index c9ccf24..a63ee71 100755
--- a/insns.pl
+++ b/insns.pl
@@ -746,9 +746,9 @@ sub byte_code_compile($$) {
             if ($op eq '66') {
                 push(@codes, 0361);
             } elsif ($op eq 'f2') {
-                push(@codes, 0362);
+                push(@codes, 0332);
             } elsif ($op eq 'f3') {
-                push(@codes, 0363);
+                push(@codes, 0333);
             } else {
                 push(@codes, 0360);
             }

[nasm:master] Drop SAME_AS flag from instruction matcher

[nasm-bot f. B. Rudiak-G. <ben...@gm...>]

Commit-ID:  6e87893f068f59929cb2d6dcc50ac1a1da2f602c
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=6e87893f068f59929cb2d6dcc50ac1a1da2f602c
Author:     Ben Rudiak-Gould <ben...@gm...>
AuthorDate: Wed, 27 Feb 2013 10:13:14 -0800
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Mon, 4 Mar 2013 00:46:16 +0400

Drop SAME_AS flag from instruction matcher

It was there to support the SSE5 DREX encoding,
which as far as I know is dead forever.

Signed-off-by: Ben Rudiak-Gould <ben...@gm...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 21 ++++-----------------
 disasm.c   | 10 ++--------
 insns.pl   | 30 +++++++++++++-----------------
 opflags.h  |  3 ---
 4 files changed, 19 insertions(+), 45 deletions(-)

diff --git a/assemble.c b/assemble.c
index 6e230ea..be3caaf 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1810,10 +1810,8 @@ static enum match_result find_match(const struct itemplate **tempp,
             /*
              * Missing operand size and a candidate for fuzzy matching...
              */
-            for (i = 0; i < temp->operands; i++) {
-                if ((temp->opd[i] & SAME_AS) == 0)
-                    xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
-            }
+            for (i = 0; i < temp->operands; i++)
+                xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
             opsizemissing = true;
         }
         if (m > merr)
@@ -1958,13 +1956,7 @@ static enum match_result matches(const struct itemplate *itemp,
      *    guess it either from template (IF_S* flag) or
      *    from code bits.
      *
-     * 2) If template operand (i) has SAME_AS flag [used for registers only]
-     *    (ie the same operand as was specified somewhere in template, and
-     *    this referred operand index is being achieved via ~SAME_AS)
-     *    we are to be sure that both registers (in template and instruction)
-     *    do exactly match.
-     *
-     * 3) If template operand do not match the instruction OR
+     * 2) If template operand do not match the instruction OR
      *    template has an operand size specified AND this size differ
      *    from which instruction has (perhaps we got it from code bits)
      *    we are:
@@ -1980,12 +1972,7 @@ static enum match_result matches(const struct itemplate *itemp,
         if (!(type & SIZE_MASK))
             type |= size[i];
 
-        if (itemp->opd[i] & SAME_AS) {
-            int j = itemp->opd[i] & ~SAME_AS;
-            if (type != instruction->oprs[j].type ||
-                instruction->oprs[i].basereg != instruction->oprs[j].basereg)
-                return MERR_INVALOP;
-        } else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
+        if (itemp->opd[i] & ~type & ~SIZE_MASK) {
             return MERR_INVALOP;
         } else if ((itemp->opd[i] & SIZE_MASK) &&
                    (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
diff --git a/disasm.c b/disasm.c
index c2b21df..89e16ab 100644
--- a/disasm.c
+++ b/disasm.c
@@ -1124,8 +1124,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
 	     * XXX: Need to make sure this is actually correct.
              */
             for (i = 0; i < (*p)->operands; i++) {
-                if (!((*p)->opd[i] & SAME_AS) &&
-		    (
+                if (
 			/* If it's a mem-only EA but we have a
 			   register, die. */
 			((tmp_ins.oprs[i].segment & SEG_RMREG) &&
@@ -1141,7 +1140,7 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
 			  (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
 			 !whichreg((*p)->opd[i],
 				   tmp_ins.oprs[i].basereg, tmp_ins.rex))
-			)) {
+			) {
                     works = false;
                     break;
                 }
@@ -1212,11 +1211,6 @@ int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
 	const operand *o = &ins.oprs[i];
 	int64_t offs;
 
-	if (t & SAME_AS) {
-	    o = &ins.oprs[t & ~SAME_AS];
-	    t = (*p)->opd[t & ~SAME_AS];
-	}
-
         output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
 
 	offs = o->offset;
diff --git a/insns.pl b/insns.pl
index e69977c..c9ccf24 100755
--- a/insns.pl
+++ b/insns.pl
@@ -433,25 +433,21 @@ sub format_insn($$$$$) {
     @ops = ();
     if ($operands ne 'void') {
         foreach $op (split(/,/, $operands)) {
-            if ($op =~ /^\=([0-9]+)$/) {
-                $op = "same_as|$1";
-            } else {
-                @opx = ();
-                foreach $opp (split(/\|/, $op)) {
-                    @oppx = ();
-                    if ($opp =~ s/(?<=\D)(8|16|32|64|80|128|256)$//) {
-                        push(@oppx, "bits$1");
-                    }
-                    $opp =~ s/^mem$/memory/;
-                    $opp =~ s/^memory_offs$/mem_offs/;
-                    $opp =~ s/^imm$/immediate/;
-                    $opp =~ s/^([a-z]+)rm$/rm_$1/;
-                    $opp =~ s/^rm$/rm_gpr/;
-                    $opp =~ s/^reg$/reg_gpr/;
-                    push(@opx, $opp, @oppx);
+            @opx = ();
+            foreach $opp (split(/\|/, $op)) {
+                @oppx = ();
+                if ($opp =~ s/(?<=\D)(8|16|32|64|80|128|256)$//) {
+                    push(@oppx, "bits$1");
                 }
-                $op = join('|', @opx);
+                $opp =~ s/^mem$/memory/;
+                $opp =~ s/^memory_offs$/mem_offs/;
+                $opp =~ s/^imm$/immediate/;
+                $opp =~ s/^([a-z]+)rm$/rm_$1/;
+                $opp =~ s/^rm$/rm_gpr/;
+                $opp =~ s/^reg$/reg_gpr/;
+                push(@opx, $opp, @oppx);
             }
+            $op = join('|', @opx);
             push(@ops, $op);
         }
     }
diff --git a/opflags.h b/opflags.h
index 1936107..4022398 100644
--- a/opflags.h
+++ b/opflags.h
@@ -239,7 +239,4 @@ typedef uint64_t opflags_t;
 #define SDWORD                  (GEN_SUBCLASS(3) | IMMEDIATE)   /* operand is in the range -0x80000000..0x7FFFFFFF */
 #define UDWORD                  (GEN_SUBCLASS(4) | IMMEDIATE)   /* operand is in the range 0..0xFFFFFFFF */
 
-/* special flags */
-#define SAME_AS                 GEN_SPECIAL(0)
-
 #endif /* NASM_OPFLAGS_H */

[nasm:master] insns: Remove pushseg/popseg internal bytecodes

[nasm-bot f. B. Rudiak-G. <ben...@gm...>]

Commit-ID:  d1ac29a3cc513642a8d42ddf964b903f5e1508d4
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=d1ac29a3cc513642a8d42ddf964b903f5e1508d4
Author:     Ben Rudiak-Gould <ben...@gm...>
AuthorDate: Sun, 3 Mar 2013 18:43:07 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sun, 3 Mar 2013 20:50:46 +0400

insns: Remove pushseg/popseg internal bytecodes

This patch is getting rid of the following bytecodes
'pushseg','popseg','pushseg2','popseg2' and simplifies
overall code.

[gorcunov@: a few style fixes]
Signed-off-by: Ben Rudiak-Gould <ben...@gm...>
Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 50 -----------------------------------------
 disasm.c   | 75 +++++++++++++++++++++++++++-----------------------------------
 insns.dat  | 16 +++++++++-----
 insns.pl   | 12 ----------
 opflags.h  | 14 ++++++++----
 regs.dat   | 10 ++++-----
 6 files changed, 58 insertions(+), 119 deletions(-)

diff --git a/assemble.c b/assemble.c
index a798d17..6e230ea 100644
--- a/assemble.c
+++ b/assemble.c
@@ -124,10 +124,6 @@
  * \340          - reserve <operand 0> bytes of uninitialized storage.
  *                 Operand 0 had better be a segmentless constant.
  * \341          - this instruction needs a WAIT "prefix"
- * \344,\345     - the PUSH/POP (respectively) codes for CS, DS, ES, SS
- *                 (POP is never used for CS) depending on operand 0
- * \346,\347     - the second byte of PUSH/POP codes for FS, GS, depending
- *                 on operand 0
  * \360          - no SSE prefix (== \364\331)
  * \361          - 66 SSE prefix (== \366\331)
  * \362          - F2 SSE prefix (== \364\332)
@@ -1050,10 +1046,6 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
                 ins->prefixes[PPS_WAIT] = P_WAIT;
             break;
 
-        case4(0344):
-            length++;
-            break;
-
         case 0360:
             break;
 
@@ -1602,48 +1594,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
         case 0341:
             break;
 
-        case 0344:
-        case 0345:
-            bytes[0] = c & 1;
-            switch (ins->oprs[0].basereg) {
-            case R_CS:
-                bytes[0] += 0x0E;
-                break;
-            case R_DS:
-                bytes[0] += 0x1E;
-                break;
-            case R_ES:
-                bytes[0] += 0x06;
-                break;
-            case R_SS:
-                bytes[0] += 0x16;
-                break;
-            default:
-                errfunc(ERR_PANIC,
-                        "bizarre 8086 segment register received");
-            }
-            out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
-            offset++;
-            break;
-
-        case 0346:
-        case 0347:
-            bytes[0] = c & 1;
-            switch (ins->oprs[0].basereg) {
-            case R_FS:
-                bytes[0] += 0xA0;
-                break;
-            case R_GS:
-                bytes[0] += 0xA8;
-                break;
-            default:
-                errfunc(ERR_PANIC,
-                        "bizarre 386 segment register received");
-            }
-            out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
-            offset++;
-            break;
-
         case 0360:
             break;
 
diff --git a/disasm.c b/disasm.c
index de80db9..c2b21df 100644
--- a/disasm.c
+++ b/disasm.c
@@ -112,50 +112,43 @@ static uint64_t getu64(uint8_t *data)
 /* Important: regval must already have been adjusted for rex extensions */
 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
 {
+    size_t i;
+
+    static const struct {
+        opflags_t       flags;
+        enum reg_enum   reg;
+    } specific_registers[] = {
+        {REG_AL,  R_AL},
+        {REG_AX,  R_AX},
+        {REG_EAX, R_EAX},
+        {REG_RAX, R_RAX},
+        {REG_DL,  R_DL},
+        {REG_DX,  R_DX},
+        {REG_EDX, R_EDX},
+        {REG_RDX, R_RDX},
+        {REG_CL,  R_CL},
+        {REG_CX,  R_CX},
+        {REG_ECX, R_ECX},
+        {REG_RCX, R_RCX},
+        {FPU0,    R_ST0},
+        {XMM0,    R_XMM0},
+        {YMM0,    R_YMM0},
+        {REG_ES,  R_ES},
+        {REG_CS,  R_CS},
+        {REG_SS,  R_SS},
+        {REG_DS,  R_DS},
+        {REG_FS,  R_FS},
+        {REG_GS,  R_GS}
+    };
+
     if (!(regflags & (REGISTER|REGMEM)))
 	return 0;		/* Registers not permissible?! */
 
     regflags |= REGISTER;
 
-    if (!(REG_AL & ~regflags))
-        return R_AL;
-    if (!(REG_AX & ~regflags))
-        return R_AX;
-    if (!(REG_EAX & ~regflags))
-        return R_EAX;
-    if (!(REG_RAX & ~regflags))
-	return R_RAX;
-    if (!(REG_DL & ~regflags))
-        return R_DL;
-    if (!(REG_DX & ~regflags))
-        return R_DX;
-    if (!(REG_EDX & ~regflags))
-        return R_EDX;
-    if (!(REG_RDX & ~regflags))
-        return R_RDX;
-    if (!(REG_CL & ~regflags))
-        return R_CL;
-    if (!(REG_CX & ~regflags))
-        return R_CX;
-    if (!(REG_ECX & ~regflags))
-        return R_ECX;
-    if (!(REG_RCX & ~regflags))
-        return R_RCX;
-    if (!(FPU0 & ~regflags))
-        return R_ST0;
-    if (!(XMM0 & ~regflags))
-	return R_XMM0;
-    if (!(YMM0 & ~regflags))
-	return R_YMM0;
-    if (!(REG_CS & ~regflags))
-        return (regval == 1) ? R_CS : 0;
-    if (!(REG_DESS & ~regflags))
-        return (regval == 0 || regval == 2
-                || regval == 3 ? nasm_rd_sreg[regval] : 0);
-    if (!(REG_FSGS & ~regflags))
-        return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
-    if (!(REG_SEG67 & ~regflags))
-        return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
+    for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
+        if (!(specific_registers[i].flags & ~regflags))
+            return specific_registers[i].reg;
 
     /* All the entries below look up regval in an 16-entry array */
     if (regval < 0 || regval > 15)
@@ -830,10 +823,6 @@ static int matches(const struct itemplate *t, uint8_t *data,
 	    dwait = 0;
 	    break;
 
-	case4(0344):
-	    ins->oprs[0].basereg = (*data++ >> 3) & 7;
-	    break;
-
 	case 0360:
 	    if (prefix->osp || prefix->rep)
 		return false;
diff --git a/insns.dat b/insns.dat
index 9e14106..99b0404 100644
--- a/insns.dat
+++ b/insns.dat
@@ -1005,9 +1005,12 @@ POP		reg64				[r:	o64nw 58+r]				X64
 POP		rm16				[m:	o16 8f /0]				8086
 POP		rm32				[m:	o32 8f /0]				386,NOLONG
 POP		rm64				[m:	o64nw 8f /0]				X64
+POP		reg_es				[-:	07]					8086,NOLONG
 POP		reg_cs				[-:	0f]					8086,UNDOC,ND
-POP		reg_dess			[-:	popseg]					8086,NOLONG
-POP		reg_fsgs			[-:	0f popseg2]				386
+POP		reg_ss				[-:	17]					8086,NOLONG
+POP		reg_ds				[-:	1f]					8086,NOLONG
+POP		reg_fs				[-:	0f a1]					386
+POP		reg_gs				[-:	0f a9]					386
 POPA		void				[	odf 61]					186,NOLONG
 POPAD		void				[	o32 61]					386,NOLONG
 POPAW		void				[	o16 61]					186,NOLONG
@@ -1054,9 +1057,12 @@ PUSH		reg64				[r:	o64nw 50+r]				X64
 PUSH		rm16				[m:	o16 ff /6]				8086
 PUSH		rm32				[m:	o32 ff /6]				386,NOLONG
 PUSH		rm64				[m:	o64nw ff /6]				X64
-PUSH		reg_cs				[-:	pushseg]				8086,NOLONG
-PUSH		reg_dess			[-:	pushseg]				8086,NOLONG
-PUSH		reg_fsgs			[-:	0f pushseg2]				386
+PUSH		reg_es				[-:	06]					8086,NOLONG
+PUSH		reg_cs				[-:	0e]					8086,NOLONG
+PUSH		reg_ss				[-:	16]					8086,NOLONG
+PUSH		reg_ds				[-:	1e]					8086,NOLONG
+PUSH		reg_fs				[-:	0f a0]					386
+PUSH		reg_gs				[-:	0f a8]					386
 PUSH		imm8				[i:	6a ib,s]					186
 PUSH		sbyteword16			[i:	o16 6a ib,s]				186,AR0,SZ,ND
 PUSH		imm16				[i:	o16 68 iw]				186,AR0,SZ
diff --git a/insns.pl b/insns.pl
index fec7ffe..e69977c 100755
--- a/insns.pl
+++ b/insns.pl
@@ -608,14 +608,6 @@ sub startseq($$) {
             return addprefix($prefix, $c1..($c1+15));
         } elsif ($c0 == 0 || $c0 == 0340) {
             return $prefix;
-        } elsif ($c0 == 0344) {
-            return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E);
-        } elsif ($c0 == 0345) {
-            return addprefix($prefix, 0x07, 0x17, 0x1F);
-        } elsif ($c0 == 0346) {
-            return addprefix($prefix, 0xA0, 0xA8);
-        } elsif ($c0 == 0347) {
-            return addprefix($prefix, 0xA1, 0xA9);
         } elsif (($c0 & ~3) == 0260 || $c0 == 0270) {
             my $c,$m,$wlp;
             $m   = shift(@codes);
@@ -694,10 +686,6 @@ sub byte_code_compile($$) {
         '!asp'      => 0365,
         'f2i'       => 0332,    # F2 prefix, but 66 for operand size is OK
         'f3i'       => 0333,    # F3 prefix, but 66 for operand size is OK
-        'pushseg'   => 0344,
-        'popseg'    => 0345,
-        'pushseg2'  => 0346,
-        'popseg2'   => 0347,
         'mustrep'   => 0336,
         'mustrepne' => 0337,
         'rex.l'     => 0334,
diff --git a/opflags.h b/opflags.h
index 2552e30..1936107 100644
--- a/opflags.h
+++ b/opflags.h
@@ -191,10 +191,16 @@ typedef uint64_t opflags_t;
 #define REG_DREG                (GEN_SUBCLASS(2) | REG_CLASS_CDT    | BITS32           | REGISTER)      /* DRn */
 #define REG_TREG                (GEN_SUBCLASS(3) | REG_CLASS_CDT    | BITS32           | REGISTER)      /* TRn */
 #define REG_SREG                (                  REG_CLASS_SREG   | BITS16           | REGISTER)      /* any segment register */
-#define REG_CS                  (GEN_SUBCLASS(1) | REG_CLASS_SREG   | BITS16           | REGISTER)      /* CS */
-#define REG_DESS                (GEN_SUBCLASS(2) | REG_CLASS_SREG   | BITS16           | REGISTER)      /* DS, ES, SS */
-#define REG_FSGS                (GEN_SUBCLASS(3) | REG_CLASS_SREG   | BITS16           | REGISTER)      /* FS, GS */
-#define REG_SEG67               (GEN_SUBCLASS(4) | REG_CLASS_SREG   | BITS16           | REGISTER)      /* Unimplemented segment registers */
+
+/* Segment registers */
+#define REG_ES                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER)      /* ES */
+#define REG_CS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER)      /* CS */
+#define REG_SS                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER)      /* SS */
+#define REG_DS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER)      /* DS */
+#define REG_FS                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* FS */
+#define REG_GS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* GS */
+#define REG_FSGS                (                  GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* FS or GS */
+#define REG_SEG67               (                  GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER)      /* Unimplemented segment registers */
 
 /* Special GPRs */
 #define REG_SMASK               SUBCLASS_MASK                                                                           /* a mask for the following */
diff --git a/regs.dat b/regs.dat
index 105c9ef..57cef6a 100644
--- a/regs.dat
+++ b/regs.dat
@@ -86,12 +86,12 @@ r8-15d	REG32NA		reg32		8
 r8-15	REG64NA		reg64		8
 
 # Segment registers
+es	REG_ES		sreg		0
 cs	REG_CS		sreg		1
-ds	REG_DESS	sreg		3
-es	REG_DESS	sreg		0
-ss	REG_DESS	sreg		2
-fs	REG_FSGS	sreg		4
-gs	REG_FSGS	sreg		5
+ss	REG_SS		sreg		2
+ds	REG_DS		sreg		3
+fs	REG_FS		sreg		4
+gs	REG_GS		sreg		5
 segr6-7	REG_SEG67	sreg		6
 
 # Control registers

[nasm:master] Move conditional opcodes close to enum ccode definition

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  83e6924e1a583d432e9a54c68a59779da5d8ce3d
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=83e6924e1a583d432e9a54c68a59779da5d8ce3d
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sun, 3 Mar 2013 14:34:31 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sun, 3 Mar 2013 14:34:31 +0400

Move conditional opcodes close to enum ccode definition

Thus if someone need to rework this code he won't need
to jump between files trying to figure out where enum
and opcodes lay.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c |  7 +------
 nasm.h     | 11 +++++++++++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/assemble.c b/assemble.c
index 7ed0892..a798d17 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1218,11 +1218,6 @@ static void gencode(int32_t segment, int64_t offset, int bits,
                     insn * ins, const struct itemplate *temp,
                     int64_t insn_end)
 {
-    static const char condval[] = {   /* conditional opcodes */
-        0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
-        0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
-        0x0, 0xA, 0xA, 0xB, 0x8, 0x4
-    };
     uint8_t c;
     uint8_t bytes[4];
     int64_t size;
@@ -1561,7 +1556,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
             break;
 
         case 0330:
-            *bytes = *codes++ ^ condval[ins->condition];
+            *bytes = *codes++ ^ get_cond_opcode(ins->condition);
             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
             offset += 1;
             break;
diff --git a/nasm.h b/nasm.h
index a9bff49..97cef3c 100644
--- a/nasm.h
+++ b/nasm.h
@@ -466,6 +466,17 @@ enum ccode { /* condition code names */
     C_none = -1
 };
 
+static inline uint8_t get_cond_opcode(enum ccode c)
+{
+    static const uint8_t ccode_opcodes[] = {
+        0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xf, 0xd, 0xc, 0xe, 0x6, 0x2,
+        0x3, 0x7, 0x3, 0x5, 0xe, 0xc, 0xd, 0xf, 0x1, 0xb, 0x9, 0x5,
+        0x0, 0xa, 0xa, 0xb, 0x8, 0x4
+    };
+
+	return ccode_opcodes[(int)c];
+}
+
 /*
  * REX flags
  */

[nasm:master] insns.pl: Various style polyshing

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  bfb581c8e00f3b159cbb67c2235bce15c5b1713a
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=bfb581c8e00f3b159cbb67c2235bce15c5b1713a
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 2 Mar 2013 02:57:58 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 2 Mar 2013 02:59:29 +0400

insns.pl: Various style polyshing

 - convert tabs to spaces
 - align octal opcodes

No func changes.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 insns.pl | 152 ++++++++++++++++++++++++++++++++-------------------------------
 1 file changed, 77 insertions(+), 75 deletions(-)

diff --git a/insns.pl b/insns.pl
index fde4f45..fec7ffe 100755
--- a/insns.pl
+++ b/insns.pl
@@ -523,19 +523,19 @@ sub decodify($$) {
     my @codes = ();
 
     unless ($codestr eq 'ignore') {
-	while ($c ne '') {
-	    if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
-		push(@codes, hex $1);
-		$c = $2;
-		next;
-	    } elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
-		push(@codes, oct $1);
-		$c = $2;
-		next;
-	    } else {
-		die "$fname: unknown code format in \"$codestr\"\n";
-	    }
-	}
+        while ($c ne '') {
+            if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
+                push(@codes, hex $1);
+                $c = $2;
+                next;
+            } elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
+                push(@codes, oct $1);
+                $c = $2;
+                next;
+            } else {
+                die "$fname: unknown code format in \"$codestr\"\n";
+            }
+        }
     }
 
     return @codes;
@@ -665,66 +665,68 @@ sub byte_code_compile($$) {
     my $opex;
 
     my %imm_codes = (
-        'ib' => 020,    # imm8
-        'ib,u' => 024,  # Unsigned imm8
-        'iw' => 030,    # imm16
-        'ib,s' => 0274, # imm8 sign-extended to opsize or bits
-        'iwd' => 034,   # imm16 or imm32, depending on opsize
-        'id' => 040,    # imm32
-        'id,s' => 0254, # imm32 sign-extended to 64 bits
-        'iwdq' => 044,  # imm16/32/64, depending on addrsize
-        'rel8' => 050,
-        'iq' => 054,
-        'rel16' => 060,
-        'rel' => 064,   # 16 or 32 bit relative operand
-        'rel32' => 070,
-        'seg' => 074,
+        'ib'        => 020,     # imm8
+        'ib,u'      => 024,     # Unsigned imm8
+        'iw'        => 030,     # imm16
+        'ib,s'      => 0274,    # imm8 sign-extended to opsize or bits
+        'iwd'       => 034,     # imm16 or imm32, depending on opsize
+        'id'        => 040,     # imm32
+        'id,s'      => 0254,    # imm32 sign-extended to 64 bits
+        'iwdq'      => 044,     # imm16/32/64, depending on addrsize
+        'rel8'      => 050,
+        'iq'        => 054,
+        'rel16'     => 060,
+        'rel'       => 064,     # 16 or 32 bit relative operand
+        'rel32'     => 070,
+        'seg'       => 074,
     );
     my %plain_codes = (
-	'o16' => 0320,		# 16-bit operand size
-	'o32' => 0321,		# 32-bit operand size
-	'odf' => 0322,		# Operand size is default
-	'o64' => 0324,		# 64-bit operand size requiring REX.W
-	'o64nw' => 0323,	# Implied 64-bit operand size (no REX.W)
-	'a16' => 0310,
-	'a32' => 0311,
-	'adf' => 0312,		# Address size is default
-	'a64' => 0313,
-	'!osp' => 0364,
-	'!asp' => 0365,
-	'f2i' => 0332,		# F2 prefix, but 66 for operand size is OK
-	'f3i' => 0333,		# F3 prefix, but 66 for operand size is OK
-	'pushseg' => 0344,
-	'popseg' => 0345,
-	'pushseg2' => 0346,
-	'popseg2' => 0347,
-	'mustrep' => 0336,
-	'mustrepne' => 0337,
-	'rex.l' => 0334,
-	'norexb' => 0314,
-	'norexx' => 0315,
-	'norexr' => 0316,
-	'norexw' => 0317,
-	'repe' => 0335,
-	'nohi' => 0325,		# Use spl/bpl/sil/dil even without REX
-	'nof3' => 0326,		# No REP 0xF3 prefix permitted
-	'norep' => 0331,	# No REP prefix permitted
-	'wait' => 0341,		# Needs a wait prefix
-	'resb' => 0340,
-	'jcc8' => 0370,		# Match only if Jcc possible with single byte
-	'jmp8' => 0371,		# Match only if JMP possible with single byte
-	'jlen' => 0373, 	# Length of jump
-	'hlexr' => 0271,
-	'hlenl' => 0272,
-	'hle' => 0273,
-	# This instruction takes XMM VSIB
-	'vsibx' => 0374,
-	'vm32x' => 0374,
-	'vm64x' => 0374,
-	# This instruction takes YMM VSIB
-	'vsiby' => 0375,
-	'vm32y' => 0375,
-	'vm64y' => 0375
+        'o16'       => 0320,    # 16-bit operand size
+        'o32'       => 0321,    # 32-bit operand size
+        'odf'       => 0322,    # Operand size is default
+        'o64'       => 0324,    # 64-bit operand size requiring REX.W
+        'o64nw'     => 0323,    # Implied 64-bit operand size (no REX.W)
+        'a16'       => 0310,
+        'a32'       => 0311,
+        'adf'       => 0312,    # Address size is default
+        'a64'       => 0313,
+        '!osp'      => 0364,
+        '!asp'      => 0365,
+        'f2i'       => 0332,    # F2 prefix, but 66 for operand size is OK
+        'f3i'       => 0333,    # F3 prefix, but 66 for operand size is OK
+        'pushseg'   => 0344,
+        'popseg'    => 0345,
+        'pushseg2'  => 0346,
+        'popseg2'   => 0347,
+        'mustrep'   => 0336,
+        'mustrepne' => 0337,
+        'rex.l'     => 0334,
+        'norexb'    => 0314,
+        'norexx'    => 0315,
+        'norexr'    => 0316,
+        'norexw'    => 0317,
+        'repe'      => 0335,
+        'nohi'      => 0325,    # Use spl/bpl/sil/dil even without REX
+        'nof3'      => 0326,    # No REP 0xF3 prefix permitted
+        'norep'     => 0331,    # No REP prefix permitted
+        'wait'      => 0341,    # Needs a wait prefix
+        'resb'      => 0340,
+        'jcc8'      => 0370,    # Match only if Jcc possible with single byte
+        'jmp8'      => 0371,    # Match only if JMP possible with single byte
+        'jlen'      => 0373,    # Length of jump
+        'hlexr'     => 0271,
+        'hlenl'     => 0272,
+        'hle'       => 0273,
+
+        # This instruction takes XMM VSIB
+        'vsibx'     => 0374,
+        'vm32x'     => 0374,
+        'vm64x'     => 0374,
+
+        # This instruction takes YMM VSIB
+        'vsiby'     => 0375,
+        'vm32y'     => 0375,
+        'vm64y'     => 0375
     );
 
     unless ($str =~ /^(([^\s:]*)\:|)\s*(.*\S)\s*$/) {
@@ -750,11 +752,11 @@ sub byte_code_compile($$) {
     my $last_imm = 'h';
     my $prefix_ok = 1;
     foreach $op (split(/\s*(?:\s|(?=[\/\\]))/, $opc)) {
-	my $pc = $plain_codes{$op};
+        my $pc = $plain_codes{$op};
 
-	if (defined $pc) {
-	    # Plain code
-	    push(@codes, $pc);
+        if (defined $pc) {
+            # Plain code
+            push(@codes, $pc);
         } elsif ($prefix_ok && $op =~ /^(66|f2|f3|np)$/) {
             # 66/F2/F3 prefix used as an opcode extension, or np = no prefix
             if ($op eq '66') {

[nasm:master] assemble: Make emit_rex being a function

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  982387606ba23004ac2df50da72cca178be642c4
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=982387606ba23004ac2df50da72cca178be642c4
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 2 Mar 2013 02:48:23 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 2 Mar 2013 02:59:29 +0400

assemble: Make emit_rex being a function

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/assemble.c b/assemble.c
index 76b147f..7ed0892 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1200,14 +1200,20 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
     return length;
 }
 
-#define EMIT_REX()                                                              \
-    if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
-        ins->rex = (ins->rex & REX_REAL)|REX_P;                                 \
-        out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);        \
-        ins->rex = 0;                                                           \
-        offset += 1;                                                            \
+static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
+{
+    if (bits == 64) {
+        if ((ins->rex & REX_REAL) && !(ins->rex & REX_V)) {
+            ins->rex = (ins->rex & REX_REAL) | REX_P;
+            out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
+            ins->rex = 0;
+            return 1;
+        }
     }
 
+    return 0;
+}
+
 static void gencode(int32_t segment, int64_t offset, int bits,
                     insn * ins, const struct itemplate *temp,
                     int64_t insn_end)
@@ -1239,7 +1245,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
         case 02:
         case 03:
         case 04:
-            EMIT_REX();
+            offset += emit_rex(ins, segment, offset, bits);
             out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
             codes += c;
             offset += c;
@@ -1252,7 +1258,7 @@ static void gencode(int32_t segment, int64_t offset, int bits,
             break;
 
         case4(010):
-            EMIT_REX();
+            offset += emit_rex(ins, segment, offset, bits);
             bytes[0] = *codes++ + (regval(opx) & 7);
             out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
             offset += 1;

[nasm:master] assemble: Use case3/4 where appropriate

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  59df421af31c930aa467232e7c0b487c3f5f5621
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=59df421af31c930aa467232e7c0b487c3f5f5621
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sun, 2 Dec 2012 02:51:18 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 2 Mar 2013 02:59:21 +0400

assemble: Use case3/4 where appropriate

This allows to shrink code a bit.

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

diff --git a/assemble.c b/assemble.c
index 0f3a338..76b147f 100644
--- a/assemble.c
+++ b/assemble.c
@@ -840,16 +840,11 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
         opex = 0;               /* For the next iteration */
 
         switch (c) {
-        case 01:
-        case 02:
-        case 03:
-        case 04:
+        case4(01):
             codes += c, length += c;
             break;
 
-        case 05:
-        case 06:
-        case 07:
+        case3(05):
             opex = c;
             break;
 
@@ -938,9 +933,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
             ins->vex_wlp = *codes++;
             break;
 
-        case 0271:
-        case 0272:
-        case 0273:
+        case3(0271):
             hleok = c & 3;
             break;
 
@@ -1064,9 +1057,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
         case 0360:
             break;
 
-        case 0361:
-        case 0362:
-        case 0363:
+        case3(0361):
             length++;
             break;
 
@@ -1079,9 +1070,7 @@ static int64_t calcsize(int32_t segment, int64_t offset, int bits,
             length++;
             break;
 
-        case 0370:
-        case 0371:
-        case 0372:
+        case3(0370):
             break;
 
         case 0373:

[nasm:master] process_ea: Drop redundant variable

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  c7ce6a4f226acd11c6b4c411a1b57ccfd05a30b1
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=c7ce6a4f226acd11c6b4c411a1b57ccfd05a30b1
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sat, 1 Dec 2012 19:38:47 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 2 Mar 2013 02:45:53 +0400

process_ea: Drop redundant variable

Signed-off-by: Cyrill Gorcunov <gor...@gm...>


---
 assemble.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/assemble.c b/assemble.c
index df0ac7d..f025360 100644
--- a/assemble.c
+++ b/assemble.c
@@ -2131,14 +2131,10 @@ static enum ea_type process_ea(operand *input, ea *output, int bits,
         /*
          * It's a direct register.
          */
-        opflags_t f;
-
         if (!is_register(input->basereg))
             goto err;
 
-        f = regflag(input);
-
-        if (!is_class(REG_EA, f))
+        if (!is_class(REG_EA, regflag(input)))
             goto err;
 
         output->rex         |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);

[nasm:master] assemble: Add case3 helper

[nasm-bot f. C. G. <gor...@gm...>]

Commit-ID:  62576a016d5681032fb66cef727b255e63234ead
Gitweb:     http://repo.or.cz/w/nasm.git?a=commitdiff;h=62576a016d5681032fb66cef727b255e63234ead
Author:     Cyrill Gorcunov <gor...@gm...>
AuthorDate: Sun, 2 Dec 2012 02:47:16 +0400
Committer:  Cyrill Gorcunov <gor...@gm...>
CommitDate: Sat, 2 Mar 2013 02:46:17 +0400

assemble: Add case3 helper

Signed-off-by: cyrill <cyrill@cyrills-MacBook-Pro.local>


---
 assemble.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/assemble.c b/assemble.c
index f025360..0f3a338 100644
--- a/assemble.c
+++ b/assemble.c
@@ -806,7 +806,8 @@ static void bad_hle_warn(const insn * ins, uint8_t hleok)
 }
 
 /* Common construct */
-#define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
+#define case3(x) case (x): case (x)+1: case (x)+2
+#define case4(x) case3(x): case (x)+3
 
 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
                         insn * ins, const struct itemplate *temp)