MyHDL 0.4 released

I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
language.

MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code. This feature provides a direct path
from Python to an FPGA or ASIC implementation.

For the details on the release, go here:

http://jandecaluwe.com/Tools/MyHDL/whatsnew04/whatsnew04.html

For a general overview and starting point, go here:

http://jandecaluwe.com/Tools/MyHDL/Overview.html

Regards, Jan