myhdl-list

[myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

On the occasion of the new release, I decided to write a
page with common situations and opinions that MyHDL addresses,
and that people hopefully can relate to.

I have tried to write it down as succinctly as possible -
hard work, takes time!

     http://www.myhdl.org/doku.php/why

Feedback, suggestions, improvements welcome!

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     From Python to silicon:
     http://www.myhdl.org

Re: [myhdl-list] Advocacy page

[Christopher L. F. <cf...@uc...>]

> On the occasion of the new release, I decided to write a
> page with common situations and opinions that MyHDL addresses,
> and that people hopefully can relate to.
>
> I have tried to write it down as succinctly as possible -
> hard work, takes time!
>
>     http://www.myhdl.org/doku.php/why
>
> Feedback, suggestions, improvements welcome!

Very good work!  Thanks for all the hard work, with the releases,  
documentation, and the "Why".


In addition to everything you mentioned in your write-up, the  
following puts all those together and captures why Python and MyHDL  
has been attractive for me.  The following isn't really new/different  
but a combination of the points you made.  Also, as you mentioned,  
putting together a coherent thought can take some time and work.  I  
apologize in advance if the following is a little sloppy:

HDL and Beyond
For any kind of algorithm work Python provides a single language where  
everything can be accomplished.  A problem can first be tackled at a  
very high level being an algorithm and / or model.  Because of  
Python's extensive libraries this work is no different than using any  
other tool.  Commonly this work and HDL implementation have be done by  
different engineers because the tools for both required a certain  
level of knowledge that wasn't transferrable between the domains.   
With Python / MyHDL an algorithm / model designer can explore HDL  
implementation and an HDL designer can explore algorithm / model  
design.  There are not multiple tools to learn.  MyHDL is an HDL  
language so the conversion from algorithm to model is still the same  
design procedure (this is a good thing) but it can all be accomplished  
in the same environment.  And the testing can be easily leveraged for  
both design domains.
--

As a side note, I have updated to the latest release and rerun a bunch  
of my MyHDL code and everything looks good so far.

[myhdl-list] IEEE STANDARDIZATION

[David B. <dav...@ya...>]

When will the final release for 0.6 be ready.  In the past, I have been having some issues with Mercurial.  I have been working them out.  However, I may need help.  Is anyone out there willing to help?
 
And Lastly,..............
 
I was wondering if MyHDL can or EVER will be submitted directly to the institute of Electronics and Electrical Engineers ( IEEE ) for obtaining UNIVERSAL and International standardization?  Where MyHDL no longer has to be converted directly to either VHDL or Verilog?  I STRONGLY believe that having to finally convert MyHDL source to Verilog or VHDL constrains the unique advantages of utilizing MyHDL within the Python programming language framework for hardware development for both FPGAs and ASICS.  
 
As an End Game Approach, the idea that I am trying to transmit is that we as a collective could write a proposal to the IEEE, where they will then develop a standardization for the MyHDL language.  The same type of standardization that has been bestowed to both Verilog and VHDL.  This would allow companies like XILINX, ALTERA, IBM, INTEL, Cadence to confident enough to develop synthesizers for MyHDL, where there would no longer be a critical need to convert MyHDL to either Verilog to VHDL.  Where a design that is not be synthesized onto an ASIC or FPGA, could be become so with this approach...
 
I believe that the National Institute of Standards and Technology (NIST) might be more than happy to bring about international standardization for MyHDL.  There is a strong need within the scientific communities to develop reconfigurable computing for numerical methods.  
 
I believe that in the end that giving MyHDL the following possible designations,
 
ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware development community.  
 
So,
 
What does everybody think about this plan.  I would love to have this plan apart of my thesis endeavor at Wright State University.  
 
 
Thanks to All,
 
David Blubaugh
 
 
 
 


      

Re: [myhdl-list] IEEE STANDARDIZATION

[Christopher L. F. <cf...@uc...>]

> When will the final release for 0.6 be ready.  In the past, I have  
> been having some issues with Mercurial.  I have been working them  
> out.  However, I may need help.  Is anyone out there willing to help?
>
> And Lastly,..............
>
> I was wondering if MyHDL can or EVER will be submitted directly to  
> the institute of Electronics and Electrical Engineers ( IEEE ) for  
> obtaining UNIVERSAL and International standardization?  Where MyHDL  
> no longer has to be converted directly to either VHDL or Verilog?  I  
> STRONGLY believe that having to finally convert MyHDL source to  
> Verilog or VHDL constrains the unique advantages of utilizing MyHDL  
> within the Python programming language framework for hardware  
> development for both FPGAs and ASICS.
>
> As an End Game Approach, the idea that I am trying to transmit is  
> that we as a collective could write a proposal to the IEEE, where  
> they will then develop a standardization for the MyHDL language.   
> The same type of standardization that has been bestowed to both  
> Verilog and VHDL.  This would allow companies like XILINX, ALTERA,  
> IBM, INTEL, Cadence to confident enough to develop synthesizers for  
> MyHDL, where there would no longer be a critical need to convert  
> MyHDL to either Verilog to VHDL.  Where a design that is not be  
> synthesized onto an ASIC or FPGA, could be become so with this  
> approach...
>
> I believe that the National Institute of Standards and Technology  
> (NIST) might be more than happy to bring about international  
> standardization for MyHDL.  There is a strong need within the  
> scientific communities to develop reconfigurable computing for  
> numerical methods.
>
> I believe that in the end that giving MyHDL the following possible  
> designations,
>


Hmmm, there is nothing stopping anyone from creating a MyHDL to gate- 
level netlist directly.  I think what Jan has done is brilliant.  He  
leveraged existing technology and tools without having to recreate a  
lot of work.  This has allowed him and others to focus on MyHDL and  
not the back end conversion.  I also think this is the correct approach.

I don't think standards are bad (not too much experience here) but I  
do think there would be a disconnect between development and the  
standardization.  Probably look at other languages for present and  
past experiences.

I think MyHDL will grow with more adoption, this requires more  
individual developers using MyHDL in their design flows and more  
success stories.

Because MyHDL outputs Verilog/VHDL it is minimal risk to add MyHDL to  
the design flow.  Personally, I like the current model.  It would be  
great to see many more developers involved and the project grow as it  
is.  As Jan has pointed out MyHDL is fully functional.  It is up to us  
developers to create some interesting works utilizing MyHDL and Python  
(I am personally working on a time reclamation tool :)

At this point there is a focal point and no competing "standards".  I  
think Jan overseeing/controlling MyHDL as the project he created is  
good.  He is very open to others comments and input.  Because of this  
MyHDL has been maturing.  There are no different/competing versions  
because company A did something different than company B.  Companies  
may become interested in MyHDL because it helps promote their tools  
(if they are good tools).


> ANSI MyHDL or ISO MyHDL, might be a benefit for the entire hadware  
> development community.
>
> So,
>
> What does everybody think about this plan.  I would love to have  
> this plan apart of my thesis endeavor at Wright State University.

As previously mentioned, I think what would help this project the most  
is more success stories and adoption.  Example for you studies if you  
were able to create a working ASIC using the MyHDL flow that would be  
very impressive (mosis education program).   You are in luck that you  
have a group of experienced developers that would help guide you in  
the usage of MyHDL.

Thanks

On Dec 17, 2008, at 6:47 AM, David Blubaugh wrote:

>
>
> Thanks to All,
>
> David Blubaugh
>
>
>
>
>
> ------------------------------------------------------------------------------
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Re: [myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
>> On the occasion of the new release, I decided to write a
>> page with common situations and opinions that MyHDL addresses,
>> and that people hopefully can relate to.
>>
>> I have tried to write it down as succinctly as possible -
>> hard work, takes time!
>>
>>     http://www.myhdl.org/doku.php/why
>>
>> Feedback, suggestions, improvements welcome!
> 
> Very good work!  Thanks for all the hard work, with the releases, 
> documentation, and the "Why".
> 
> 
> In addition to everything you mentioned in your write-up, the following 
> puts all those together and captures why Python and MyHDL has 
> been attractive for me.  The following isn't really new/different but 
> a combination of the points you made.  

Thanks, I think this is a very valid case that I hadn't listed yet.
I have reworded it and added to the advocacy page:

http://www.myhdl.org/doku.php/why#you_would_like_to_do_algorithm_development_and_implementation_in_the_same_environment

Thanks,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html

Re: [myhdl-list] Advocacy page

[Andrew S. <g.a...@gm...>]

How about "because you can take your dev env (MyHDL/gtkwave/emacs for
me) with you"?  I'm a noob at hardware design so maybe you all do not
find this so advantageous but for me its a pain to use the WebPack ISE
GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
device I'm going to have to learn Quartus I think?  With MyHDL I can
do all the simulation outside of the vendor GUI and so all I have to
learn to do in each vendor tool is how to click the "compile" button,
assign the pins, and program the device, instead of trying to actually
use GUIs that seem to be designed by a bunch of hardware engineers
;-).

Now I do my MyHDL programming in Linux, and then I only pop up a
Windows VM when I want to program the device.

Andrew

On Wed, Dec 17, 2008 at 5:24 AM, Jan Decaluwe <ja...@ja...> wrote:
> On the occasion of the new release, I decided to write a
> page with common situations and opinions that MyHDL addresses,
> and that people hopefully can relate to.
>
> I have tried to write it down as succinctly as possible -
> hard work, takes time!
>
>     http://www.myhdl.org/doku.php/why
>
> Feedback, suggestions, improvements welcome!
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     From Python to silicon:
>     http://www.myhdl.org
>
>
> ------------------------------------------------------------------------------
> SF.Net email is Sponsored by MIX09, March 18-20, 2009 in Las Vegas, Nevada.
> The future of the web can't happen without you.  Join us at MIX09 to help
> pave the way to the Next Web now. Learn more and register at
> http://ad.doubleclick.net/clk;208669438;13503038;i?http://2009.visitmix.com/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Advocacy page

[Christopher F. <cf...@uc...>]

  find this so advantageous but for me its a pain to use the WebPack
>ISE
> GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
> device I'm going to have to learn Quartus I think?  With MyHDL I can
> do all the simulation outside of the vendor GUI and so all I have to
> learn to do in each vendor tool is how to click the "compile" 
>button,
> assign the pins, and program the device, instead of trying to 
>actually
> use GUIs that seem to be designed by a bunch of hardware engineers

I believe you can get a python script from Dillon Engineering site 
that will run the synthesis for most these FPGA tools.  If not all of 
them, the framework is there shouldn't be hard to add.  That way no 
need to learn guis for each of the vendors.

Good luck.

Re: [myhdl-list] Advocacy page

[Martin d A. <po...@ma...>]

On Wed, 17 Dec 2008, Christopher Felton wrote:
>> use GUIs that seem to be designed by a bunch of hardware engineers
>
> That way no need to learn guis for each of the vendors.

One thing I learned quickly in ASIC design and verification is to stay 
away from vendor GUIs and always use command line tools (except for 
waveforms viewing, I don't see much choice here). I use GNU Make to 
implement the dependencies and bash to tie the pieces together. You also 
need a good load sharing/job dispatching tool.

Martin

Re: [myhdl-list] Advocacy page

[Günter D. <dan...@we...>]

Christopher Felton wrote:
...
> 
> I believe you can get a python script from Dillon Engineering site 
> that will run the synthesis for most these FPGA tools.  If not all of 
> them, the framework is there shouldn't be hard to add.  That way no 
> need to learn guis for each of the vendors.

I have ran that script with a 10.x version of ISE recently and noticed
that it does not work anymore. After spending some time with debugging I
noticed that ISE has now a feature to export the project settings to a
tcl script. I haven't followed up on that function, but believe that
could be an all command line way to run an ISE implementation.

Guenter

Re: [myhdl-list] Advocacy page

[Jan D. <ja...@ja...>]

Andrew Stone wrote:
> How about "because you can take your dev env (MyHDL/gtkwave/emacs for
> me) with you"?  I'm a noob at hardware design so maybe you all do not
> find this so advantageous but for me its a pain to use the WebPack ISE
> GUI for Xilinx chips, Flex for Cypress, and if I ever get an Altera
> device I'm going to have to learn Quartus I think?  With MyHDL I can
> do all the simulation outside of the vendor GUI and so all I have to
> learn to do in each vendor tool is how to click the "compile" button,
> assign the pins, and program the device, instead of trying to actually
> use GUIs that seem to be designed by a bunch of hardware engineers
> ;-).

I don't think we can argue that MyHDL has a clear distincitive advantage
for non-GUI based design. You can set it up for other HDL languages
and environments also. (When I was doing Verilog and VHDL, I have
basically always done it like that.)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html