myhdl-list

[myhdl-list] [PATCH 0 of 3 ] toVHDL: indentation and documentation placement improvements

[Angel E. <ang...@gm...>]

This patch series addresses a few of the small issues that I recently discussedon this mailing list.
Please have a look at them and let me know if they are acceptable (in content and coding style).

[myhdl-list] [PATCH 1 of 3] toVHDL: improve indentation of type definitions

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349882135 -7200
# Branch 0.8-dev
# Node ID 3c6f870ae4b826ac462778d3d61a6477928957ef
# Parent  41d4a8b1380479a3c93e2ecbf7cb90f7dc955119
toVHDL: improve indentation of type definitions

Up until now the indentation of type definitions was be wrong. VHDL type
definitions span multiple lines but only only their first line was indented.

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -222,7 +222,7 @@
     _sortedEnumTypeList = list(_enumTypeSet)
     _sortedEnumTypeList.sort(cmp=lambda a, b: cmp(a._name, b._name))
     for t in _sortedEnumTypeList:
-        print >> f, "    %s" % t._toVHDL()
+        print >> f, "    %s" % t._toVHDL().replace('\n', '\n    ')
     print >> f
     print >> f, "end package pck_%s;" % intf.name
     print >> f

[myhdl-list] [PATCH 2 of 3] toVHDL: indent signal declarations

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349882392 -7200
# Branch 0.8-dev
# Node ID 54652ce766a4f8ee6318e662a5394df20a899711
# Parent  3c6f870ae4b826ac462778d3d61a6477928957ef
toVHDL: indent signal declarations

It is common practice to indent signal declarations (e.g. VHDL indent tools
often indent them). This also makes the generated VHDL code a bit cleaner.

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -303,7 +303,7 @@
                               )
             # the following line implements initial value assignments
             # print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
-            print >> f, "signal %s: %s%s;" % (s._name, p, r)
+            print >> f, "    signal %s: %s%s;" % (s._name, p, r)
         elif s._read:
             # the original exception
             # raise ToVHDLError(_error.UndrivenSignal, s._name)
@@ -312,7 +312,7 @@
                           category=ToVHDLWarning
                           )
             constwires.append(s)
-            print >> f, "signal %s: %s%s;" % (s._name, p, r)
+            print >> f, "    signal %s: %s%s;" % (s._name, p, r)
     for m in memlist:
         if not m._used:
             continue
@@ -327,8 +327,8 @@
         r = _getRangeString(m.elObj)
         p = _getTypeString(m.elObj)
         t = "t_array_%s" % m.name
-        print >> f, "type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
-        print >> f, "signal %s: %s;" % (m.name, t)
+        print >> f, "    type %s is array(0 to %s-1) of %s%s;" % (t, m.depth, p, r)
+        print >> f, "    signal %s: %s;" % (m.name, t)
     print >> f
 
 def _writeCompDecls(f,  compDecls):

[myhdl-list] [PATCH 3 of 3] toVHDL: place entity documentation above the entity declaration

[Angel E. <ang...@gm...>]

# HG changeset patch
# User Angel Ezquerra <ang...@gm...>
# Date 1349882593 -7200
# Branch 0.8-dev
# Node ID 58ac2e97c7efbe7e3c9784b8ac25218daa056e40
# Parent  54652ce766a4f8ee6318e662a5394df20a899711
toVHDL: place entity documentation above the entity declaration

Up until now the entity documentation was placed betweent he entity and the
architecture, which is an unusual location for entity level documentation.

diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -241,6 +241,7 @@
     if needPck:
         print >> f, "use %s.pck_%s.all;" % (lib, intf.name)
         print >> f
+    print >> f, doc
     print >> f, "entity %s is" % intf.name
     if intf.argnames:
         f.write("    port (")
@@ -273,7 +274,6 @@
                 f.write("\n        %s: in %s%s" % (portname, p, r))
         f.write("\n    );\n")
     print >> f, "end entity %s;" % intf.name
-    print >> f, doc
     print >> f
     print >> f, "architecture %s of %s is" % (arch, intf.name)
     print >> f