myhdl-list

[myhdl-list] Inconsistency between simulation and conversion

[Nicolas P. <nic...@aa...>]

Hi,

When using this statement "counter.next += 1" I get an error when 
converting my design to VHDL :

myhdl.ConversionError: in file 
Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
     Not supported: Augmented signal assignment

This makes sense.
However, this same statement does not trig any error when simulating the 
design.
Is this the intended behaviour ?

Nicolas


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Re: [myhdl-list] Inconsistency between simulation and conversion

[Christopher F. <chr...@gm...>]

On 4/28/16 1:54 AM, Nicolas Pinault wrote:
> Hi,
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51: Â Â Â  Not
> supported: Augmented signal assignment
>
> This makes sense. However, this same statement does not trig any
> error when simulating the design. Is this the intended behaviour ?

I believe it is expected, only a subset is convertible.
You would not want to error on non-convertible statements
because they could be useful for modeling and test
(i.e. non-conversion).

The manual doesn't state one way or the other for signal
assignments, we should add that the *augmented* assignment
operators are not supported for signal assignments:
http://docs.myhdl.org/en/stable/manual/conversion.html#signal-assignment

Regards,
Chris

Re: [myhdl-list] Inconsistency between simulation and conversion

[Henry G. <he...@ma...>]

On 28/04/16 07:54, Nicolas Pinault wrote:
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
> 
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
> 
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
> 

Incrementing .next is a slightly odd thing to want to do, but is
possible given .next is likely an int type. Clearly it doesn't really
make sense from the perspective of conversion.

Henry

Re: [myhdl-list] Inconsistency between simulation and conversion

[Samuele D. <sm...@gm...>]

On Thu, Apr 28, 2016 at 1:47 PM, Henry Gomersall <he...@ma...> wrote:

> On 28/04/16 07:54, Nicolas Pinault wrote:
> > When using this statement "counter.next += 1" I get an error when
> > converting my design to VHDL :
> >
> > myhdl.ConversionError: in file
> > Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
> >     Not supported: Augmented signal assignment
> >
> > This makes sense.
> > However, this same statement does not trig any error when simulating the
> > design.
> > Is this the intended behaviour ?
> >
>
> Incrementing .next is a slightly odd thing to want to do,


I would remove slightly to the sentence :).
You are supposed to do "counter.next = counter+1" and not "counter.next =
counter.next+1"

Simulation in MyHDL is just execution of your code and you are allowed to
do nasty things!

Samuele

Re: [myhdl-list] [EXT] Re: Inconsistency between simulation and conversion

[David S. <dst...@kc...>]

This makes me wonder, in simulation is it actually incrementing counter.next, or is it incrementing the value of counter?

It doesn’t feel like having augmented operators work the way most people would expect (counter.next +=1 -> counter.next = counter + 1) is going to cause anyone any actual problem. Am I missing something? Or is it just harder to make work correctly than it’s worth?

Dave

From: Samuele Disegna [mailto:sm...@gm...]
Sent: Thursday, April 28, 2016 7:13 AM
To: General discussions on MyHDL
Subject: [EXT] Re: [myhdl-list] Inconsistency between simulation and conversion

On Thu, Apr 28, 2016 at 1:47 PM, Henry Gomersall <he...@ma...<mailto:he...@ma...>> wrote:
On 28/04/16 07:54, Nicolas Pinault wrote:
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>

Incrementing .next is a slightly odd thing to want to do,

I would remove slightly to the sentence :).
You are supposed to do "counter.next = counter+1" and not "counter.next = counter.next+1"

Simulation in MyHDL is just execution of your code and you are allowed to do nasty things!

Samuele
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Re: [myhdl-list] Inconsistency between simulation and conversion

[Christopher F. <chr...@gm...>]

On Thu, Apr 28, 2016 at 7:12 AM, Samuele Disegna <sm...@gm...> wrote:

> On Thu, Apr 28, 2016 at 1:47 PM, Henry Gomersall <he...@ma...> wrote:
>
>> On 28/04/16 07:54, Nicolas Pinault wrote:
>> > When using this statement "counter.next += 1" I get an error when
>> > converting my design to VHDL :
>> >
>> > myhdl.ConversionError: in file
>> > Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>> >     Not supported: Augmented signal assignment
>> >
>> > This makes sense.
>> > However, this same statement does not trig any error when simulating the
>> > design.
>> > Is this the intended behaviour ?
>> >
>>
>> Incrementing .next is a slightly odd thing to want to do,
>
>
> I would remove slightly to the sentence :).
> You are supposed to do "counter.next = counter+1" and not "counter.next =
> counter.next+1"
>
> Simulation in MyHDL is just execution of your code and you are allowed to
> do nasty things!
>
> Samuele
>

Absolutely, well stated.  We shouldn't increment the "next" but
assigning "next" to "current (val) + 1".  The augmented does't make
sense.

Regards,
Chris

Re: [myhdl-list] Inconsistency between simulation and conversion

[Nicolas P. <nic...@aa...>]

Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
> On 28/04/16 07:54, Nicolas Pinault wrote:
>> When using this statement "counter.next += 1" I get an error when
>> converting my design to VHDL :
>>
>> myhdl.ConversionError: in file
>> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>>      Not supported: Augmented signal assignment
>>
>> This makes sense.
>> However, this same statement does not trig any error when simulating the
>> design.
>> Is this the intended behaviour ?
>>
> Incrementing .next is a slightly odd thing to want to do, but is
> possible given .next is likely an int type. Clearly it doesn't really
> make sense from the perspective of conversion.
To be consistent, I expect simulation to raise an exception as 
conversion does.

Nicolas

>
> Henry
>
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>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
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Re: [myhdl-list] Inconsistency between simulation and conversion

[Samuele D. <sm...@gm...>]

Ok, "counter.next +=1" is not equivalent to "counter.next = counter+1".
Is it really true that most people expect that equivalence?

.next  is a python property that gives to you the intbv object
counter._next. That object will be incremented.
This makes sense to me.

Anyway while checking MyHDL sources I spotted a little bug:

at line 546
https://github.com/jandecaluwe/myhdl/blob/master/myhdl/_Signal.py
"def _augm(self)" should be  "_augm(self,arg)"
# augmented assignment not supported
def _augm(self):
raise TypeError("Signal object doesn't support augmented assignment")
__iadd__ = __isub__ = __imul__ = __ipow__ = __imod__ = _augm
__ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm
__itruediv__ = __ifloordiv__ = _augm

On Thu, Apr 28, 2016 at 3:05 PM, Nicolas Pinault <nic...@aa...> wrote:

> Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>
> On 28/04/16 07:54, Nicolas Pinault wrote:
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>
>
> Incrementing .next is a slightly odd thing to want to do, but is
> possible given .next is likely an int type. Clearly it doesn't really
> make sense from the perspective of conversion.
>
> To be consistent, I expect simulation to raise an exception as conversion
> does.
>
> Nicolas
>
>
>
> Henry
>
> ------------------------------------------------------------------------------
> Find and fix application performance issues faster with Applications Manager
> Applications Manager provides deep performance insights into multiple tiers of
> your business applications. It resolves application problems quickly and
> reduces your MTTR. Get your free trial!https://ad.doubleclick.net/ddm/clk/302982198;130105516;z
> _______________________________________________
> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>
>
>
>
> --
>
>
> * Nicolas PINAULT R&D electronics engineer * ni...@aa...
>
> *AATON-Digital*
> 38000 Grenoble - France
> Tel +33 4 7642 9550
>
> http://www.aaton.com
> http://www.transvideo.eu
> French Technologies for Film and Digital Cinematography
>
> Follow us on Twitter
> @Aaton_Digital
> @Transvideo_HD
>
> Like us on Facebook
> https://www.facebook.com/AatonDigital
>
>
>
> ------------------------------------------------------------------------------
> Find and fix application performance issues faster with Applications
> Manager
> Applications Manager provides deep performance insights into multiple
> tiers of
> your business applications. It resolves application problems quickly and
> reduces your MTTR. Get your free trial!
> https://ad.doubleclick.net/ddm/clk/302982198;130105516;z
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Inconsistency between simulation and conversion

[Christopher F. <chr...@gm...>]

On Thu, Apr 28, 2016 at 8:05 AM, Nicolas Pinault <nic...@aa...> wrote:

> Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>
> On 28/04/16 07:54, Nicolas Pinault wrote:
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>
>
> Incrementing .next is a slightly odd thing to want to do, but is
> possible given .next is likely an int type. Clearly it doesn't really
> make sense from the perspective of conversion.
>
> To be consistent, I expect simulation to raise an exception as conversion
> does.
>
>
Hmmm, might require some conversation.  Nothing would
prevent someone from incrementing (augmenting) next in
modeling or verification - kinda odd but not sure if it should
throw and error.

Regards,
Chris

Re: [myhdl-list] Inconsistency between simulation and conversion

[Nicolas P. <nic...@aa...>]

Le 28/04/2016 à 18:45, Christopher Felton a écrit :
>
>
> On Thu, Apr 28, 2016 at 8:05 AM, Nicolas Pinault <nic...@aa... 
> <mailto:nic...@aa...>> wrote:
>
>     Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>>     On 28/04/16 07:54, Nicolas Pinault wrote:
>>>     When using this statement "counter.next += 1" I get an error when
>>>     converting my design to VHDL :
>>>
>>>     myhdl.ConversionError: in file
>>>     Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>>>          Not supported: Augmented signal assignment
>>>
>>>     This makes sense.
>>>     However, this same statement does not trig any error when simulating the
>>>     design.
>>>     Is this the intended behaviour ?
>>>
>>     Incrementing .next is a slightly odd thing to want to do, but is
>>     possible given .next is likely an int type. Clearly it doesn't really
>>     make sense from the perspective of conversion.
>     To be consistent, I expect simulation to raise an exception as
>     conversion does.
>
>
> Hmmm, might require some conversation.  Nothing would
> prevent someone from incrementing (augmenting) next in
> modeling or verification - kinda odd but not sure if it should
> throw and error.
Well, at least, a warning should be generated when simulating.
I used augmented assignment inadvertently in a module. I made all the 
development with it without any problem. Then I got an error when 
converting. At first, this was a big surprise. I quickly found (and 
understood) the source of the problem but I would have preferred to be 
aware of the problem during simulation.
At first, I don't see any useful case of augmenting next attribute, even 
in simulation.

Nicolas
>
> Regards,
> Chris
>
>
> ------------------------------------------------------------------------------
> Find and fix application performance issues faster with Applications Manager
> Applications Manager provides deep performance insights into multiple tiers of
> your business applications. It resolves application problems quickly and
> reduces your MTTR. Get your free trial!
> https://ad.doubleclick.net/ddm/clk/302982198;130105516;z
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
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Follow us on Twitter
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