myhdl-list

[myhdl-list] Thanks for MyHDL & PLL's

[Mr C C. <ch...@be...>]

I'm genuinely pleasantly surprised by how much difference MyHDL make to 
the ease of use and general accessibility of FPGA's (you never know 
manufacturers might be so impressed they send you all their internal 
docs ;) - okay you can stop laughing now - but wouldn't they sell more 
chips? )

My previous experience has been with some 6GB monstrosity of a tool 
chain and well... it just wasn't fun, using MyHDL and Icestorm is a very 
much more pleasant and productive experience

Thanks!

One thing I can't seem to find any info about - what do I do with the 
icepll output

here's a verilog example
https://github.com/SubProto/icestick-vga-test/blob/master/vga.v

how do I replicate the SB_PLL40_CORE and instance it in python (MyHDL)

if that isn't possible, could someone give me an example wrapped in a 
custom verilog clause?

on the 8k board how do you instance both PLL's - do you have to do 
anything specific if you want to use both sources and also feed one into 
the other?

Once again thanks for MyHDL, fantastic work!

C

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Christopher F. <chr...@gm...>]

>
> One thing I can't seem to find any info about - what do I do with the
> icepll output
>
> here's a verilog example
> https://github.com/SubProto/icestick-vga-test/blob/master/vga.v
>
> how do I replicate the SB_PLL40_CORE and instance it in python (MyHDL)
>
> if that isn't possible, could someone give me an example wrapped in a
> custom verilog clause?

This isn't a minimilistic example or an iCE PLL example
but it is an example of wrapping a Xilinx MMCM
https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py

Regards,
Chris

>
> on the 8k board how do you instance both PLL's - do you have to do
> anything specific if you want to use both sources and also feed one into
> the other?

No you shouldn't have to do anything special, just
instance the two PLLs and connect as you want.

Regards,
Chris

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Christopher F. <chr...@gm...>]

>>
>> if that isn't possible, could someone give me an example wrapped in a
>> custom verilog clause?
>
> This isn't a minimilistic example or an iCE PLL example
> but it is an example of wrapping a Xilinx MMCM
> https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py
>

Here is an example wrapping an iCE40 (?) `SB_IO`:
https://github.com/xesscorp/CAT-Board/blob/master/tests/ice40_primitives.py

Regards,
Chris

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Mr C C. <ch...@be...>]

 >This isn't a minimilistic example or an iCE PLL example but it is an 
example of wrapping a Xilinx >MMCM 
https://github.com/cfelton/rhea/blob/master/rhea/vendor/xilinx/_device_clock_mgmt.py 
 >Regards, Chris

lol - yeah ya not kidding it's going to take me this side of next month 
just to figure out how to get that working!!!

Don't suppose you've got a saner example of including a verilog module 
within a MyHDL do you? it's either way less complex than it looks or I'm 
missing something here!

thx
Chris

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Jan C. <jen...@mu...>]

On Thu, 25 Feb 2016 21:03:22 +0000
Mr C Camacho <ch...@be...> wrote:

> Don't suppose you've got a saner example of including a
> verilog module within a MyHDL do you? it's either way less
> complex than it looks or I'm missing something here!

I have wrapped Lattice library components to make them simulate
or export for synthesis.

The smallest wrapper I have is for a Lattice XO2 internal osc
- 47 lines. 

Have also an iCE40 SB_RAM256X16.py with initialization, which I
have used. 

I also started wrapping everything from the iCE40 primitive
library, thinking I might ignore the synthesis tool and do it all
in MyHDL, but most of this is untested. 

Have you noticed that the icestorm tools can program an iCE40
part in just 2s?

Let me know if you'd like anything emailed. 

Jan Coombs. 
-- 
email valid at present...

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Mr C C. <ch...@be...>]

yeah the icestorm tools are sweet, programming just the cram is a nice 
option and blisteringly fast :)

the combination of MyHDL and icestorm is nice...

mind I have noticed some oddities for example comparing list/tuple intbv 
elements with a intbv is still defeating me... I guess I'm still trying 
to get my head round the subtleties !

On 25/02/16 22:39, Jan Coombs wrote:
> On Thu, 25 Feb 2016 21:03:22 +0000
> Mr C Camacho <ch...@be...> wrote:
>
>> Don't suppose you've got a saner example of including a
>> verilog module within a MyHDL do you? it's either way less
>> complex than it looks or I'm missing something here!
> I have wrapped Lattice library components to make them simulate
> or export for synthesis.
>
> The smallest wrapper I have is for a Lattice XO2 internal osc
> - 47 lines.
>
> Have also an iCE40 SB_RAM256X16.py with initialization, which I
> have used.
>
> I also started wrapping everything from the iCE40 primitive
> library, thinking I might ignore the synthesis tool and do it all
> in MyHDL, but most of this is untested.
>
> Have you noticed that the icestorm tools can program an iCE40
> part in just 2s?
>
> Let me know if you'd like anything emailed.
>
> Jan Coombs.

Re: [myhdl-list] Thanks for MyHDL & PLL's

[Edward V. <dev...@sb...>]

Hi All
I too have been working with C. Felton and Dave Vandenbout https://hackaday.io/project/7982-cat-board

who developed the CAT-Board for the Raspberry Pi.  

Some of the things work okay with the yosys-tools. 

 My RPi2B with CatBoard are running in my home.
http://99.184.183.104/video.webm  The Catboard was program with the yosys tools.

For my catboard_blinky_host I had to use iCECube2 from Lattice.
This use C. Felton rhea and myhdl to generate the verilog code.

https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/input_examples/catboard_blinky_host.py

One of the things that I find really great is myhdl simulation.
python test_catboard_blinky_host.py --trace & python test_catboard_blinky_host.py --build
 wc iceriver/catboard.v
 1221  3131 35222 iceriver/catboard.v
If you have any question let me know. 

Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Thursday, February 25, 2016 3:46 PM, Mr C Camacho <ch...@be...> wrote:
 

 yeah the icestorm tools are sweet, programming just the cram is a nice 
option and blisteringly fast :)

the combination of MyHDL and icestorm is nice...

mind I have noticed some oddities for example comparing list/tuple intbv 
elements with a intbv is still defeating me... I guess I'm still trying 
to get my head round the subtleties !

On 25/02/16 22:39, Jan Coombs wrote:
> On Thu, 25 Feb 2016 21:03:22 +0000
> Mr C Camacho <ch...@be...> wrote:
>
>> Don't suppose you've got a saner example of including a
>> verilog module within a MyHDL do you? it's either way less
>> complex than it looks or I'm missing something here!
> I have wrapped Lattice library components to make them simulate
> or export for synthesis.
>
> The smallest wrapper I have is for a Lattice XO2 internal osc
> - 47 lines.
>
> Have also an iCE40 SB_RAM256X16.py with initialization, which I
> have used.
>
> I also started wrapping everything from the iCE40 primitive
> library, thinking I might ignore the synthesis tool and do it all
> in MyHDL, but most of this is untested.
>
> Have you noticed that the icestorm tools can program an iCE40
> part in just 2s?
>
> Let me know if you'd like anything emailed.
>
> Jan Coombs.


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Re: [myhdl-list] Thanks for MyHDL & PLL's

[Christopher F. <chr...@gm...>]

On 2/25/2016 4:46 PM, Mr C Camacho wrote:
>
> mind I have noticed some oddities for example comparing list/tuple
> intbv elements with a intbv is still defeating me... I guess I'm
> still trying to get my head round the subtleties !

It might be worthwhile reviewing the a couple of the
conversion sections - how the list-of-signals and
list-of-tuples is mapped for conversion:


http://docs.myhdl.org/en/stable/manual/conversion_examples.html#ram-inference
http://docs.myhdl.org/en/stable/manual/conversion_examples.html#rom-inference

For the ROM, often you need to get the item from
the ROM first before.  The following is a demonstration,
the first compare doesn't convert the second does
https://gist.github.com/cfelton/d9d6bf4f6ff4c4afbed2

Regards,
Chris