myhdl-list

[myhdl-list] A module that connects signals if names match

[Ben R. <be...@re...>]

Hi all,

I'm experimenting with MyHDL and am trying to write a module that connects
inputs and outputs based on the signals names.  I doing this to get a feel
for what MyHDL can and cannot do.

The code is at https://gist.github.com/benreynwar/5963c2658883322be7c4
including the generated verilog.

The module "Reduces" takes a generic input interface, and a generic output
interface.  All signals which have the same name in both the input and
output interface are connected.
Any other signals are ignored.

It simulates without complaining but does not give the output I would
expect.  The outputs remain unchanged.

It generates verilog without error, but the generated verilog does not
match what I would expect.

I expect I'm going about this wrong, since I have little experience with
MyHDL.  Any pointers would be appreciated.

Cheers,
Ben

Re: [myhdl-list] A module that connects signals if names match

[Ben R. <be...@re...>]

And five minutes after posting I found a bug in my code that explained why
the simulation wasn't working.  I had inputs and outputs wrong way round!
However, I still am having issues with the verilog generation.

On Wed, Feb 24, 2016 at 8:54 PM, Ben Reynwar <be...@re...> wrote:

> Hi all,
>
> I'm experimenting with MyHDL and am trying to write a module that connects
> inputs and outputs based on the signals names.  I doing this to get a feel
> for what MyHDL can and cannot do.
>
> The code is at https://gist.github.com/benreynwar/5963c2658883322be7c4
> including the generated verilog.
>
> The module "Reduces" takes a generic input interface, and a generic output
> interface.  All signals which have the same name in both the input and
> output interface are connected.
> Any other signals are ignored.
>
> It simulates without complaining but does not give the output I would
> expect.  The outputs remain unchanged.
>
> It generates verilog without error, but the generated verilog does not
> match what I would expect.
>
> I expect I'm going about this wrong, since I have little experience with
> MyHDL.  Any pointers would be appreciated.
>
> Cheers,
> Ben
>

Re: [myhdl-list] A module that connects signals if names match

[Christopher F. <chr...@gm...>]

On 2/24/2016 10:00 PM, Ben Reynwar wrote:
> And five minutes after posting I found a bug in my code that
> explained why the simulation wasn't working.  I had inputs and
> outputs wrong way round! However, I still am having issues with the
> verilog generation.


It looks like it is working, what is the issue you are
having?

There is a known side-effect when converting top-level
interface ports.  When converting the interfaces some
name-mangling occurs, the Python compiler does this
renaming.

Regards,
Chris

Re: [myhdl-list] A module that connects signals if names match

[Ben R. <be...@re...>]

Thanks for the help Chris.  I've updated the code so that I have 3 input
signals (i_a, i_b, i_c) and 2 output signals (o_b, o_c).

The name mangling converts both i_b and i_c to i, and both o_b and o_c to
o.  How should I get around this issue?

On Thu, Feb 25, 2016 at 6:49 AM, Christopher Felton <chr...@gm...>
wrote:

> On 2/24/2016 10:00 PM, Ben Reynwar wrote:
> > And five minutes after posting I found a bug in my code that
> > explained why the simulation wasn't working.  I had inputs and
> > outputs wrong way round! However, I still am having issues with the
> > verilog generation.
>
>
> It looks like it is working, what is the issue you are
> having?
>
> There is a known side-effect when converting top-level
> interface ports.  When converting the interfaces some
> name-mangling occurs, the Python compiler does this
> renaming.
>
> Regards,
> Chris
>
>
>
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>

Re: [myhdl-list] A module that connects signals if names match

[Christopher F. <chr...@gm...>]

On 2/25/2016 8:34 AM, Ben Reynwar wrote:
> Thanks for the help Chris.  I've updated the code so that I have 3 input
> signals (i_a, i_b, i_c) and 2 output signals (o_b, o_c).
>
> The name mangling converts both i_b and i_c to i, and both o_b and o_c to
> o.  How should I get around this issue?
>

This seems to be a bug, I did an explicit version [1]
and and got similar results:

     def top_level_assign(intf_in, intf_out):
         m1 = assign(intf_in.b, intf_out.b)
         m2 = assign(intf_in.c, intf_out.c)
         return  m1, m2

     module top_level_assign (
         b,
         b,
         a,
         a,
         intf_in_a
     );

There might be an issue created for this already, I
need to check (vaguely recall discussing something
similar in the past).  If not an issue should be
created.

Regards,
Chris

[1] https://gist.github.com/cfelton/81c680347dc6b2d5a458

Re: [myhdl-list] A module that connects signals if names match

[Ben R. <be...@re...>]

Thanks.  I have faint memories of running into something similar last time
I played with MyHDL about a year ago, so it's possible it was me running
into it last time!  Is the use of interfaces still fairly uncommon in
MyHDL, or are they pretty mainstream now?

On Thu, Feb 25, 2016 at 8:14 AM, Christopher Felton <chr...@gm...>
wrote:

> On 2/25/2016 8:34 AM, Ben Reynwar wrote:
> > Thanks for the help Chris.  I've updated the code so that I have 3 input
> > signals (i_a, i_b, i_c) and 2 output signals (o_b, o_c).
> >
> > The name mangling converts both i_b and i_c to i, and both o_b and o_c to
> > o.  How should I get around this issue?
> >
>
> This seems to be a bug, I did an explicit version [1]
> and and got similar results:
>
>      def top_level_assign(intf_in, intf_out):
>          m1 = assign(intf_in.b, intf_out.b)
>          m2 = assign(intf_in.c, intf_out.c)
>          return  m1, m2
>
>      module top_level_assign (
>          b,
>          b,
>          a,
>          a,
>          intf_in_a
>      );
>
> There might be an issue created for this already, I
> need to check (vaguely recall discussing something
> similar in the past).  If not an issue should be
> created.
>
> Regards,
> Chris
>
> [1] https://gist.github.com/cfelton/81c680347dc6b2d5a458
>
>
>
>
>
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>

Re: [myhdl-list] A module that connects signals if names match

[Christopher F. <chr...@gm...>]

On 2/25/2016 10:30 AM, Ben Reynwar wrote:
> Thanks.  I have faint memories of running into something similar last time
> I played with MyHDL about a year ago, so it's possible it was me running
> into it last time!  Is the use of interfaces still fairly uncommon in
> MyHDL, or are they pretty mainstream now?
>

I use interfaces all the time, to me it is critical.
But I do not use top-level interfaces, I only use
them in the design.  I typically write a wrapper
for MyHDL modules that I use as submodules in a
larger mixed HDL design.

Interfaces in the design are mainstream!  There are
issues with interface top-level conversion, at first
we were not going to include top-level conversion
(kinda like list-of-signals).  One of the reasons
things might not of changed in this area is because
of the MEP114 addition (@myhdl.module), meaning that
this issue has been (will be) put on the back burner
until MEP114 is merged into master.

Regards,
Chris

Re: [myhdl-list] A module that connects signals if names match

[Ben R. <be...@re...>]

That makes sense.  So when I'm experimenting with things like this, I can
write a generic modules using interfaces, but when testing it, wrap it with
an explicit module so that I don't have any interfaces in my top-level.
Thanks again for your help.

Cheers,
Ben

On Thu, Feb 25, 2016 at 9:53 AM, Christopher Felton <chr...@gm...>
wrote:

> On 2/25/2016 10:30 AM, Ben Reynwar wrote:
> > Thanks.  I have faint memories of running into something similar last
> time
> > I played with MyHDL about a year ago, so it's possible it was me running
> > into it last time!  Is the use of interfaces still fairly uncommon in
> > MyHDL, or are they pretty mainstream now?
> >
>
> I use interfaces all the time, to me it is critical.
> But I do not use top-level interfaces, I only use
> them in the design.  I typically write a wrapper
> for MyHDL modules that I use as submodules in a
> larger mixed HDL design.
>
> Interfaces in the design are mainstream!  There are
> issues with interface top-level conversion, at first
> we were not going to include top-level conversion
> (kinda like list-of-signals).  One of the reasons
> things might not of changed in this area is because
> of the MEP114 addition (@myhdl.module), meaning that
> this issue has been (will be) put on the back burner
> until MEP114 is merged into master.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] A module that connects signals if names match

[Christopher F. <chr...@gm...>]

On 2/25/2016 11:00 AM, Ben Reynwar wrote:
> That makes sense.  So when I'm experimenting with things like this,
> I can write a generic modules using interfaces, but when testing it,
> wrap it with an explicit module so that I don't have any interfaces
> in my top-level.

Yes, that is a recipe for success :)

I will do things like the following to make the
explicit ports in the top-levels easier to manage

     def my_core_top(
         # somewhat painful explicitly listing the ports
         # ...
     )
     portmap = dict(clock=Signal(bool(0))
     portmap.update(axi4lite_portmap)
     my_core_top.portmap = portmap

In my testbenches and conversion scripts I don't
need to type out all those ports again

     portmap = my_core_top.portmap
     clock = portmap['clock']
     axi = AXI4LiteInterface(portmap)
     tbdut = my_core_top(**portmap)

To me this makes sense because a top-level maps to
an explicit static hardware device, having tools to
map the explicit portmap to the generic interfaces
is a good approach, in my opinion.

Regards,
Chris