myhdl-list

[myhdl-list] (rhea) icestick_blinky_host.py

[Edward V. <dev...@sb...>]

Hi All,I am trying to add these memmap_command_bridge,  glbl_timer_ticks, Barebone and FIFOBus
cores from (rhea) icestick_blinky_host.py  to my code.
On the CAT-Board on pg 6 of the schematic the 100MHz oscillator provides 

signal USER_CLK which is connected to C8 of ICE40-HX8K-CT256.

The catboard.pcf created with rhea, in the catboard.pcf file I see set_io clock C8.

Do these 2 lines above have an impact on the ICE40 clock?
 
clock=Clock(0, frequency=50e6)
glbl = Global(clock, None) 

Running python input_clk.py --convert generates cat_top.v.Running python input_clk.py --build generates iceriver/catboard.v
In the catboard.v I see wire cmd_inst_clock; which is not in cat_top.v.
Also many of the modules in catboard.v have this linealways @(posedge cmd_inst_clock) begin
What drives cmd_inst_clock?
https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/input_examples/input_clk.py
 Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] (rhea) icestick_blinky_host.py

[Christopher F. <chr...@gm...>]

On 2/5/2016 11:05 AM, Edward Vidal wrote:
> Hi All,I am trying to add these memmap_command_bridge,
> glbl_timer_ticks, Barebone and FIFOBus cores from (rhea)
> icestick_blinky_host.py  to my code. On the CAT-Board on pg 6 of the
> schematic the 100MHz oscillator provides
>
> signal USER_CLK which is connected to C8 of ICE40-HX8K-CT256.
>
> The catboard.pcf created with rhea, in the catboard.pcf file I see
> set_io clock C8.
>
> Do these 2 lines above have an impact on the ICE40 clock?
>
> clock=Clock(0, frequency=50e6) glbl = Global(clock, None)

Yes, they would but it would be an unexpected effect.  If
you are using the rhea.build, it will map the ports to
the board definitions - as long as the port names match
the pin names (which are typically the names from the
schematic / documents).

You can see in the CAT board definition this is already
defined: 
<https://github.com/cfelton/rhea/blob/master/rhea/build/boards/lattice/_catboard.py#L18>
This will be mapped to the `clock` port in your top-level
module.  So it should "just work" :)

The idea, if designing for a specific board you will have
a top-level for that board:

     def my_cat_design(clock, led, sw):
         # you might want to do more, like debounce,
         # sync, etc.
	reset = sw(0)  # sw[0] reset, get shadow signal
         glbl = Global(clock, reset)

Do note, when I tested the `memmap_command_bridge` on the
icestick it did not work with iceriver (yosys+aracne+icestorm)
but it did work with the icecube2.

Hope that helps,
Chris

Re: [myhdl-list] (rhea) icestick_blinky_host.py

[Edward V. <dev...@sb...>]

Hi All,

My concern was the setting the frequency to 50e6.  Is this just for the UART since it has a baud rate?
In the xula2.ucf I do see 
NET "clock" TNM_NET = "clock"; 
TIMESPEC "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%;which is the 12MHz of the XulA2 board
While on the catboard.pcf I never see anything related to timing.
Running python input_clk.py --convert generates cat_top.v.Running python input_clk.py --build generates iceriver/catboard.v
In the catboard.v I see wire cmd_inst_clock; which is not in cat_top.v.
Also many of the modules in catboard.v have this linealways @(posedge cmd_inst_clock) begin
What drives cmd_inst_clock? Thanks
Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Friday, February 5, 2016 1:25 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 2/5/2016 11:05 AM, Edward Vidal wrote:
> Hi All,I am trying to add these memmap_command_bridge,
> glbl_timer_ticks, Barebone and FIFOBus cores from (rhea)
> icestick_blinky_host.py  to my code. On the CAT-Board on pg 6 of the
> schematic the 100MHz oscillator provides
>
> signal USER_CLK which is connected to C8 of ICE40-HX8K-CT256.
>
> The catboard.pcf created with rhea, in the catboard.pcf file I see
> set_io clock C8.
>
> Do these 2 lines above have an impact on the ICE40 clock?
>
> clock=Clock(0, frequency=50e6) glbl = Global(clock, None)

Yes, they would but it would be an unexpected effect.  If
you are using the rhea.build, it will map the ports to
the board definitions - as long as the port names match
the pin names (which are typically the names from the
schematic / documents).

You can see in the CAT board definition this is already
defined: 
<https://github.com/cfelton/rhea/blob/master/rhea/build/boards/lattice/_catboard.py#L18>
This will be mapped to the `clock` port in your top-level
module.  So it should "just work" :)

The idea, if designing for a specific board you will have
a top-level for that board:

    def my_cat_design(clock, led, sw):
        # you might want to do more, like debounce,
        # sync, etc.
    reset = sw(0)  # sw[0] reset, get shadow signal
        glbl = Global(clock, reset)

Do note, when I tested the `memmap_command_bridge` on the
icestick it did not work with iceriver (yosys+aracne+icestorm)
but it did work with the icecube2.

Hope that helps,
Chris


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Re: [myhdl-list] (rhea) icestick_blinky_host.py

[Christopher F. <chr...@gm...>]

On 2/5/16 3:02 PM, Edward Vidal wrote:
> Hi All,
>
>
> My concern was the setting the frequency to 50e6.  Is this just for
> the UART since it has a baud rate?

I am confused, why or how are you setting it
to 50e6?  Like I said before you should just
be using the clock passed during the build
so you shouldn't have to set it.

>
> In the xula2.ucf I do see NET "clock" TNM_NET = "clock"; TIMESPEC
> "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%; which is the
> 12MHz of the XulA2 board
 >
 > While on the catboard.pcf I never see anything related to timing.
 >

The clock constraints should be written out for
the ice flow (iceriver) as well.  I forget if
this is something that has not been implemented
yet or not supported in arachne.

In this case, correct the frequency is used for
for any time based things: buad, 1 second tick,
etc.

> Running python input_clk.py --convert generates cat_top.v. Running
> python input_clk.py --build generates iceriver/catboard.v
>
> In the catboard.v I see wire cmd_inst_clock; which is not in
> cat_top.v.
>
> Also many of the modules in catboard.v have this line always
> @(posedge cmd_inst_clock) begin

If you don't think it is correct you would have
to trace it out in the Verilog source.  Name
changes do occur in conversion.  If your simulation
tests pass it is probably ok and name changes
occurred in the conversion.

Regards,
Chris