Thread: [myhdl-list] adding files to top-level with rhea
Brought to you by:
jandecaluwe
Menu
▾
▴
myhdl-list
|
From: Edward V. <dev...@sb...> - 2015-12-21 16:05:19
|
Modifications to blink.py on RPi2B used to create catboard.bin.
--- blink.py 2015-12-14 11:03:16.519999868 +0000
+++ blink.py.tmp 2015-12-14 11:02:09.009999894 +0000
@@ -9,12 +9,12 @@
nled = len(led)
maxcnt = int(clock.frequency)
- cnt = Signal(intbv(0,min=0,max=maxcnt))
+ cnt = Signal(intbv(0,min=0,max=12000000))
toggle = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl():
- if cnt == maxcnt-1:
+ if cnt == 12000000:
cnt.next = 0
toggle.next = not toggle
else:
Modifications to blink.py on Ubuntu used to create xula2.bit.
--- blink.py 2015-12-21 05:47:24.931919453 -0700
+++ blink.py.tmp 2015-12-21 05:47:09.387919627 -0700
@@ -9,12 +9,12 @@
nled = len(led)
maxcnt = int(clock.frequency)
- cnt = Signal(intbv(0,min=0,max=maxcnt))
+ cnt = Signal(intbv(0,min=0,max=1440000))
toggle = Signal(bool(0))
@always_seq(clock.posedge, reset=reset)
def rtl():
- if cnt == maxcnt-1:
+ if cnt == 1440000:
cnt.next = 0
toggle.next = not toggle
else:
Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
the same rate as leds on CAT-Board with RPi2B.
|
|
From: Christopher F. <chr...@gm...> - 2015-12-23 16:16:06
|
On 12/21/15 10:05 AM, Edward Vidal wrote:
> Hello All,
>
> Yosys & arachne-pnr appear to work very well compared to Xilinx ISE.
> It takes 2:41 to generate xula2.bit, while it only takes 0:35 to
> generate the catboard.bin.
>
Not to diminish the efforts of the open-source
synthesis and PaR but run-time is a small
benefit when compared to the resource and
timing results. In other-words, if the flow
executes quickly but uses twice as many
resources it isn't a good comparison.
> On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
> See the changes to blink.py in the file attached chgs_blink.txt.
> I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
> Using 1440000 on the XulA2-LX9 would be 8.333333 times.
> Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
> the same rate as leds on CAT-Board with RPi2B.
>
I haven't looked at your code, one thing you
might want to do is verify your design works
with the IceCub2 as well as Yosys+Ar, in
my testing I have had icestick designs work
with IceCube and not with Yosys. I plan on
adding the IceCub2 flow to the rhea.build but
it is farther down on my list of things to do.
> I generated the docs in both html & latexpdf formats.
>
> Running make in rhea/test appears to work okay.
> The test_models/test_fx2_model.py just hangs up. Should the be expected
> at this point?
Yes, there seems to be an issue with py.test
that I haven't figured out yet. If you run
`make test` it will run all the same tests
but not using py.test.
>
> In the file ex_xula2.py I added the flow.add_files line.
> flow.add_files('jpeg_cat.v')
> flow.run()
> Running ISE I see the file jpeg_cat.v is now part of the project.
> What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
> Or do I have to do this manually?
You have to do this manually, there is an
undocumented (beta) feature that might help
(`verilog_instance`) otherwise the documented
approach is to us `verilog_code` and create a
wrapper for the module you want instantiate.
>
> Does anyone have a MyHDL or Verilog for a DCM?
> I have been using the one in Xess VHDL_Lib
>
I have been slowly adding some vendor agnostic
primitives to rhea, one of these is a clock
manager (PLL/DCM/MMCM):
https://github.com/cfelton/rhea/blob/master/examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py#L20
But I have only limited testing, you might
not want to use it unless you are willing to
debug and make changes.
Regards,
Chris
|
|
From: Edward V. <dev...@sb...> - 2015-12-23 21:00:16
|
make test
rm -Rf output/
mkdir output/
/usr/bin/time python ./test_cores/test_converters/test_adc128s022.py > output/run_all_tests.log
0.20user 0.01system 0:00.22elapsed 99%CPU (0avgtext+0avgdata 44912maxresident)k
0inputs+8outputs (0major+3121minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_eth/test_gemac_lite.py >> output/run_all_tests.log
0.01user 0.00system 0:00.01elapsed 94%CPU (0avgtext+0avgdata 21344maxresident)k
0inputs+0outputs (0major+1460minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_afifo.py >> output/run_all_tests.log
2.24user 0.01system 0:02.26elapsed 99%CPU (0avgtext+0avgdata 43648maxresident)k
0inputs+0outputs (0major+3032minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_ffifo.py >> output/run_all_tests.log
0.13user 0.01system 0:00.14elapsed 99%CPU (0avgtext+0avgdata 42816maxresident)k
0inputs+0outputs (0major+2978minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_fifo_ramp.py >> output/run_all_tests.log
20.45user 0.01system 0:20.48elapsed 99%CPU (0avgtext+0avgdata 44048maxresident)k
0inputs+416outputs (0major+3055minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_sfifo.py >> output/run_all_tests.log
5.69user 0.01system 0:05.71elapsed 99%CPU (0avgtext+0avgdata 46288maxresident)k
0inputs+0outputs (0major+3195minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_sdram/test_sdram.py >> output/run_all_tests.log
0.26user 0.02system 0:00.29elapsed 99%CPU (0avgtext+0avgdata 58672maxresident)k
0inputs+0outputs (0major+4254minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_serio.py >> output/run_all_tests.log
0.21user 0.01system 0:00.23elapsed 100%CPU (0avgtext+0avgdata 41552maxresident)k
0inputs+0outputs (0major+2896minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_spi.py >> output/run_all_tests.log
0.22user 0.02system 0:00.25elapsed 99%CPU (0avgtext+0avgdata 73008maxresident)k
0inputs+8outputs (0major+5161minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_ticks.py >> output/run_all_tests.log
1.56user 0.01system 0:01.58elapsed 99%CPU (0avgtext+0avgdata 41856maxresident)k
0inputs+0outputs (0major+2924minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_video/test_create_image.py >> output/run_all_tests.log
Traceback (most recent call last):
File "./test_cores/test_video/test_create_image.py", line 27, in <module>
test_create_save()
File "./test_cores/test_video/test_create_image.py", line 23, in test_create_save
disp.set_pixel(col, row, rgb, last)
File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 105, in set_pixel
self.create_save_image()
File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 139, in create_save_image
print(" width ........... {}".format(im.width))
File "/usr/lib/python2.7/dist-packages/PIL/Image.py", line 515, in __getattr__
raise AttributeError(name)
AttributeError: width
Error in sys.excepthook:
Traceback (most recent call last):
File "/usr/lib/python2.7/dist-packages/apport_python_hook.py", line 66, in apport_excepthook
from apport.fileutils import likely_packaged, get_recent_crashes
File "/usr/lib/python2.7/dist-packages/apport/__init__.py", line 1, in <module>
from apport.report import Report
File "/usr/lib/python2.7/dist-packages/apport/report.py", line 20, in <module>
import apport.fileutils
File "/usr/lib/python2.7/dist-packages/apport/fileutils.py", line 22, in <module>
from apport.packaging_impl import impl as packaging
File "/usr/lib/python2.7/dist-packages/apport/packaging_impl.py", line 20, in <module>
import apt
File "/usr/lib/python2.7/dist-packages/apt/__init__.py", line 21, in <module>
import apt_pkg
ImportError: /opt/Xilinx/14.6/ISE_DS/ISE/lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/python2.7/dist-packages/apt_pkg.so)
Original exception was:
Traceback (most recent call last):
File "./test_cores/test_video/test_create_image.py", line 27, in <module>
test_create_save()
File "./test_cores/test_video/test_create_image.py", line 23, in test_create_save
disp.set_pixel(col, row, rgb, last)
File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 105, in set_pixel
self.create_save_image()
File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 139, in create_save_image
print(" width ........... {}".format(im.width))
File "/usr/lib/python2.7/dist-packages/PIL/Image.py", line 515, in __getattr__
raise AttributeError(name)
AttributeError: width
Command exited with non-zero status 1
2.20user 0.04system 0:02.24elapsed 99%CPU (0avgtext+0avgdata 218304maxresident)k
0inputs+0outputs (0major+15170minor)pagefaults 0swaps
make: *** [test] Error 1
|
|
From: Christopher F. <chr...@gm...> - 2015-12-23 23:57:43
|
Edward,
The the Xula2 already exists, you can use the
Xula2.
from rhea.build.boards.xilinx import Xula2
https://github.com/cfelton/rhea/blob/master/rhea/build/boards/xilinx/__init__.py#L4
Regards,
Chris
On Wed, Dec 23, 2015 at 3:00 PM, Edward Vidal <dev...@sb...>
wrote:
> Chris,
> I see what you did with my_board_def.py. The problem I am having is in
> the file
> rhea/rhea/build/boards/xilinx/_xula.py device = 'XC6SLX25'. I need to
> override to device = 'XC6SLX9'.
> There are 2 versions xula2.
>
> I tried make test instead of make.
> Thanks,
>
>
>
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> On Wednesday, December 23, 2015 9:16 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>
> On 12/21/15 10:05 AM, Edward Vidal wrote:
> > Hello All,
> >
> > Yosys & arachne-pnr appear to work very well compared to Xilinx ISE.
> > It takes 2:41 to generate xula2.bit, while it only takes 0:35 to
> > generate the catboard.bin.
> >
>
> Not to diminish the efforts of the open-source
> synthesis and PaR but run-time is a small
> benefit when compared to the resource and
> timing results. In other-words, if the flow
> executes quickly but uses twice as many
> resources it isn't a good comparison.
>
> > On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
> > See the changes to blink.py in the file attached chgs_blink.txt.
> > I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
> > Using 1440000 on the XulA2-LX9 would be 8.333333 times.
> > Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
> > the same rate as leds on CAT-Board with RPi2B.
> >
>
> I haven't looked at your code, one thing you
> might want to do is verify your design works
> with the IceCub2 as well as Yosys+Ar, in
> my testing I have had icestick designs work
> with IceCube and not with Yosys. I plan on
> adding the IceCub2 flow to the rhea.build but
> it is farther down on my list of things to do.
>
> > I generated the docs in both html & latexpdf formats.
> >
> > Running make in rhea/test appears to work okay.
> > The test_models/test_fx2_model.py just hangs up. Should the be expected
> > at this point?
>
> Yes, there seems to be an issue with py.test
> that I haven't figured out yet. If you run
> `make test` it will run all the same tests
> but not using py.test.
>
> >
> > In the file ex_xula2.py I added the flow.add_files line.
> > flow.add_files('jpeg_cat.v')
> > flow.run()
> > Running ISE I see the file jpeg_cat.v is now part of the project.
> > What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
> > Or do I have to do this manually?
>
> You have to do this manually, there is an
> undocumented (beta) feature that might help
> (`verilog_instance`) otherwise the documented
> approach is to us `verilog_code` and create a
> wrapper for the module you want instantiate.
>
>
> >
> > Does anyone have a MyHDL or Verilog for a DCM?
> > I have been using the one in Xess VHDL_Lib
> >
>
> I have been slowly adding some vendor agnostic
> primitives to rhea, one of these is a clock
> manager (PLL/DCM/MMCM):
>
> https://github.com/cfelton/rhea/blob/master/examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py#L20
>
> But I have only limited testing, you might
> not want to use it unless you are willing to
> debug and make changes.
>
> Regards,
> Chris
>
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
|
×
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.
Thanks for helping keep SourceForge clean.
X