myhdl-list

[myhdl-list] rhea AssertionError

[Edward V. <dev...@sb...>]

Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board

My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
python buttons_display.py creates buttons_display.v with my signals and
module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA 
pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.

How do you add a port to a signal not connected to a pin?

I have tried brd.add_port('left_i', 'NONE') for my signals.

python ex_catboard_buttons.py 
Traceback (most recent call last):
  File "ex_catboard_buttons.py", line 53, in <module>
    run_catboard()
  File "ex_catboard_buttons.py", line 49, in run_catboard
    flow.run()
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_iceriver.py", line 84, in run
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_convert.py", line 30, in convert
  File "build/bdist.linux-armv7l/egg/rhea/build/_fpga.py", line 239, in get_portmap
AssertionError: Error unspecified port left_i


Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] rhea AssertionError

[Christopher F. <chr...@gm...>]

On 12/17/2015 10:15 AM, Edward Vidal wrote:
> Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board
>
> My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
> python buttons_display.py creates buttons_display.v with my signals and
> module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA
> pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.
>
> How do you add a port to a signal not connected to a pin?
>

You can't at least not with the current implementation.
The FPGA toolflow automation assumes you are building
for a particular development board, all top-level ports
need to be assigned to a pin.

It doesn't preclude you from creating a design with any
combination for ports just from automatically mapping a
top-level module to an FPGA board.

The main goal of the tool automation is to take a top-level
MyHDL design and automatically map it to a development
board.  If the port names don't match the pin names in
the dev board definition (typically the names from the
documentation) then there is some work to manually map
the ports to pins.

Now, if you don't really want to target a dev board but
want to see if a module will synthesize - this is currently
not support but it is something I can possibly add with
little effort.

Hope that helps,
Chris

Re: [myhdl-list] rhea AssertionError

[Edward V. <dev...@sb...>]

Hi Chris,Is blinky consided a top level?
I have a XulA2-LX9, do I just modify the   line 39 in _xula.py   device = 'XC6SLX9' -->    device = 'XC6SLX9'?Or should we define a new class?
I  tested on ubuntu 12.04 with Xilinx 14.6.  All appears to work okay.  Only one led was tested.
Should  blinky where I start with the CAT-Board also?Should the ice40_primitives.py be included as part of rhea?Regards,
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Thursday, December 17, 2015 9:52 AM, Christopher Felton <chr...@gm...> wrote:
 

 On 12/17/2015 10:15 AM, Edward Vidal wrote:
> Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board
>
> My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
> python buttons_display.py creates buttons_display.v with my signals and
> module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA
> pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.
>
> How do you add a port to a signal not connected to a pin?
>

You can't at least not with the current implementation.
The FPGA toolflow automation assumes you are building
for a particular development board, all top-level ports
need to be assigned to a pin.

It doesn't preclude you from creating a design with any
combination for ports just from automatically mapping a
top-level module to an FPGA board.

The main goal of the tool automation is to take a top-level
MyHDL design and automatically map it to a development
board.  If the port names don't match the pin names in
the dev board definition (typically the names from the
documentation) then there is some work to manually map
the ports to pins.

Now, if you don't really want to target a dev board but
want to see if a module will synthesize - this is currently
not support but it is something I can possibly add with
little effort.

Hope that helps,
Chris




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Re: [myhdl-list] rhea AssertionError

[Christopher F. <chr...@gm...>]

On 12/17/2015 9:12 PM, Edward Vidal wrote:
> Hi Chris,Is blinky consided a top level? I have a XulA2-LX9, do I
> just modify the   line 39 in _xula.py   device = 'XC6SLX9' -->
> device = 'XC6SLX9'?Or should we define a new class?

No, ideally you do not modify _xula.py file.  The
Xula2 itself does not have any LEDs, so the board
definition only includes the generic channel (IO)
ports.

I added some documentation and an example that shows
how to create a custom board definition:
docs: http://rhearay.readthedocs.org/en/latest/build/board_definition.html
example: 
https://github.com/cfelton/rhea/tree/master/examples/boards/xula/custom

> I  tested on
> ubuntu 12.04 with Xilinx 14.6.  All appears to work okay.  Only one
> led was tested. Should  blinky where I start with the CAT-Board
> also?Should the ice40_primitives.py be included as part of
> rhea?Regards,

I haven't looked at your ice40_primitives yet, yes
a version of it can be included in rhea.  I have
been trying to create vendor neutral primitives,
I will look over (at some point) you ice40_primitives
and see if I can use it in that approach.

Regards,
Chris