Thread: [myhdl-list] co-simuation
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From: Edward V. <dev...@sb...> - 2015-08-31 17:26:07
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Hello All, I am testing VHD2VL and trying to test the outputted file ifchain.v with MyHDL & Iverilog co-simulation on a Raspberry Pi 2 B. I created the files and folder vcd https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd The above files were based on Chris Felton alt.hdl that I had forked and tested on Raspberry Pi 2 B https://github.com/develone/alt.hdl/tree/master/examples/ex2_mathadds/test_verilogs git clone https://github.com/develone/alt.hdl.git cd alt.hdl/examples/ex2_mathadds/test_verilogs/ cp ~/raspberrypi2_yocto/vhd2vl/examples/tb/myhdl.vpi . mkdir vcd python test_mathadds.py This producee the expected output. The output in next few lines below between the *** are to verify GTKWAVE, MyHDL & Iverilog work with a Co-Simulation on Raspberry Pi 2 B. ******************************************************************* python test_mathadds.py compiling ... *iverilog -o mathadds ../myhdl/mm_maths1.v ../bsv/mb_maths1.v ../bsv/mkMaths1.v ../chisel/generated/mc_maths1.v ./tb_mathadds.v cosimulation setup ... VCD info: dumpfile vcd/maths1.vcd opened for output. start (co)simulation ... 33: [ 0, 0] mb 0, mc 0, mm 0 [20] 34: [ 1, 1] mb 20, mc 20, mm 20 [20] 35: [ 1, 1] mb 20, mc 20, mm 20 [20] 36: [ 1, 1] mb 20, mc 20, mm 20 [20] 37: [ 1, 1] mb 20, mc 20, mm 20 [5300] 38: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 39: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 40: [ 543, -13] mb 5300, mc 5300, mm 5300 [5300] 41: [ 543, -13] mb 5300, mc 5300, mm 5300 [-50] 42: [ -7, 2] mb -50, mc -50, mm -50 [-50] 43: [ -7, 2] mb -50, mc -50, mm -50 [-50] 44: [ -7, 2] mb -50, mc -50, mm -50 [-50] 45: [ -7, 2] mb -50, mc -50, mm -50 [630010] 46: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] 47: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] 48: [ 31000, 32001] mb -25350, mc -25350, mm -25350 [630010] In addition the gtkwave vcd/maths1.vcd shows the expected signal changes ******************************************************************* If in stimlus section of test_ifchain.py. I comment the lines 25 & 26 I get the results below. python test_ifchain.py Running test... 0 *{'a': Signal(intbv(0L)), 'status': Signal(False), 'b': Signal(intbv(0L)), compiling ... iverilog -o ifchain ../ifchain.v ./tb_ifchain.v cosimulation setup ... vvp -m ./myhdl.vpi ifchain VCD info: dumpfile vcd/ifchain1.vcd opened for output. <myhdl._Cosimulation.Cosimulation object at 0x769f6870> back from prep cosim start (co)simulation ... This appears to work okay but when I gtkwave vcd/ifchain1.vcd The signals a,b and clk red and status is yellow. When the I uncomment lines 25 & 26 try send values to the co-simulation. The program does not run to completion but crashes with the following error. File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Waiter.py", line 142, in next clause = next(self.generator) File "test_ifchain.py", line 25, in stimlus a.next = 10 Not be an experienced co-simulation user I asked if anyone can provide me insight into this problem. Thanks in advance. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
From: Christopher F. <chr...@gm...> - 2015-08-31 17:46:38
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<snip> > > I created the files and folder vcd > https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb > > ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd > Did you build the myhdl.vpi locally on the machine you are running? Regards, Chris |
From: Edward V. <dev...@sb...> - 2015-08-31 18:08:03
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Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation. If you are testing on non arm system this should be replaced by the one created on your system. I maybe should have not added it to the github repository. Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote: <snip> > > I created the files and folder vcd > https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb > > ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd > Did you build the myhdl.vpi locally on the machine you are running? Regards, Chris ------------------------------------------------------------------------------ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2015-08-31 18:21:10
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On 8/31/2015 1:07 PM, Edward Vidal wrote: > Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation. If you are testing on non arm system this should be replaced by the one created on your system. > I maybe should have not added it to the github repository. You might want to try running it on a desktop system first, that way you can isolate system/OS issues. Quickly reviewing the code nothing jumps out. My next step to test it on an x86 desktop linux. I have to admit, I am a little confused why you are running the toolflow on the RPi2 - what is the goal? Regards, Chris > Thanks > Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 > > > On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote: > > > <snip> >> >> I created the files and folder vcd >> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb >> >> ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd >> > > Did you build the myhdl.vpi locally on the machine > you are running? > > Regards, > Chris > > > > ------------------------------------------------------------------------------ > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > > > ------------------------------------------------------------------------------ > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |
From: Edward V. <dev...@sb...> - 2015-08-31 18:51:15
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Chris,I did run this on the a Ubuntu 12.04 on an AMD processor. I get the same results as on the Pi. Dave is working on Lattice ICE-40 board for the Pi and I wanted to get some tools working on the Pi. So far I have I been able to get GTKWave, Myhdl, Iverilog, vhd2vl, FireFox, Python 2.7 & Python3, XSTOOLs(XuLA2-LX), samba and OpenCV on the Pi. The O/S for the Pi was created with Yocto which creates a custom Linux Distro and the supporting cross compiler.Also a tool which is needed but not running on the Pi is Yosys which is the tool used to generate the bit file for the Lattice ICE-40. This would in turn createa standalone HDL development system at a low cost. Dave indicates the XSTOOLs will not be needed for Lattice ICE-40. The bit file will be downloaded using GPIO instead of the USB. Dave tweeted last week that the board was almost ready. I hope I stated everything correctly. If you have any questions let me know. Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Monday, August 31, 2015 12:24 PM, Christopher Felton <chr...@gm...> wrote: On 8/31/2015 1:07 PM, Edward Vidal wrote: > Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation. If you are testing on non arm system this should be replaced by the one created on your system. > I maybe should have not added it to the github repository. You might want to try running it on a desktop system first, that way you can isolate system/OS issues. Quickly reviewing the code nothing jumps out. My next step to test it on an x86 desktop linux. I have to admit, I am a little confused why you are running the toolflow on the RPi2 - what is the goal? Regards, Chris > Thanks > Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 > > > On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote: > > > <snip> >> >> I created the files and folder vcd >> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb >> >> ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd >> > > Did you build the myhdl.vpi locally on the machine > you are running? > > Regards, > Chris > > > > ------------------------------------------------------------------------------ > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > > > ------------------------------------------------------------------------------ > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > ------------------------------------------------------------------------------ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2015-09-01 14:02:20
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On 8/31/2015 12:25 PM, Edward Vidal wrote: > Hello All, > I am testing VHD2VL and trying to test the outputted file ifchain.v with MyHDL & Iverilog > co-simulation on a Raspberry Pi 2 B. > > I created the files and folder vcd > https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb > > ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd > <snip> > If in stimlus section of test_ifchain.py. > I comment the lines 25 & 26 I get the results below. > > python test_ifchain.py > Running test... > 0 > *{'a': Signal(intbv(0L)), 'status': Signal(False), 'b': Signal(intbv(0L)), > compiling ... > iverilog -o ifchain ../ifchain.v ./tb_ifchain.v > cosimulation setup ... > vvp -m ./myhdl.vpi ifchain > VCD info: dumpfile vcd/ifchain1.vcd opened for output. > <myhdl._Cosimulation.Cosimulation object at 0x769f6870> > back from prep cosim > start (co)simulation ... > > This appears to work okay but when I gtkwave vcd/ifchain1.vcd > The signals a,b and clk red and status is yellow. > > When the I uncomment lines 25 & 26 try send values to the co-simulation. > The program does not run to completion but crashes with the following error. > File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Waiter.py", line 142, in next > clause = next(self.generator) > File "test_ifchain.py", line 25, in stimlus > a.next = 10 > This actually is not a cosimulation error. I ran your code and the resulting error is: ValueError: intbv value 10 >= maximum 8 In your code your `a` and `b` are: a = Signal(intbv(0)[3:]) b = Signal(intbv(0)[3:]) Now remember, in Python the upper limit is exclusive, you created 3bit bit-vectors. The max value that can be used is 7. You probably intended it to be: a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) When I make the changes, you code executes without error. Regards, Chris |
From: Edward V. <dev...@sb...> - 2015-09-01 19:06:00
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Chris,Thanks for the information. That helped me.My vcd/ifchain.vcd is starting to show signs of life. I am trying to document my process. Can you take a look at the 2 files below and give me ideas on what is right and what is wrong. https://github.com/develone/raspberrypi2_yocto/blob/master/doc/simulate.pdf and https://github.com/develone/raspberrypi2_yocto/blob/master/doc/tb_xxxx.pdf Still not getting the status to go green in my co-simulation.I just push my latest code to github.Thanks Regards Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, September 1, 2015 8:03 AM, Christopher Felton <chr...@gm...> wrote: On 8/31/2015 12:25 PM, Edward Vidal wrote: > Hello All, > I am testing VHD2VL and trying to test the outputted file ifchain.v with MyHDL & Iverilog > co-simulation on a Raspberry Pi 2 B. > > I created the files and folder vcd > https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb > > ifchain myhdl.vpi tb_ifchain.v test_ifchain.py vcd > <snip> > If in stimlus section of test_ifchain.py. > I comment the lines 25 & 26 I get the results below. > > python test_ifchain.py > Running test... > 0 > *{'a': Signal(intbv(0L)), 'status': Signal(False), 'b': Signal(intbv(0L)), > compiling ... > iverilog -o ifchain ../ifchain.v ./tb_ifchain.v > cosimulation setup ... > vvp -m ./myhdl.vpi ifchain > VCD info: dumpfile vcd/ifchain1.vcd opened for output. > <myhdl._Cosimulation.Cosimulation object at 0x769f6870> > back from prep cosim > start (co)simulation ... > > This appears to work okay but when I gtkwave vcd/ifchain1.vcd > The signals a,b and clk red and status is yellow. > > When the I uncomment lines 25 & 26 try send values to the co-simulation. > The program does not run to completion but crashes with the following error. > File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Waiter.py", line 142, in next > clause = next(self.generator) > File "test_ifchain.py", line 25, in stimlus > a.next = 10 > This actually is not a cosimulation error. I ran your code and the resulting error is: ValueError: intbv value 10 >= maximum 8 In your code your `a` and `b` are: a = Signal(intbv(0)[3:]) b = Signal(intbv(0)[3:]) Now remember, in Python the upper limit is exclusive, you created 3bit bit-vectors. The max value that can be used is 7. You probably intended it to be: a = Signal(intbv(0)[4:]) b = Signal(intbv(0)[4:]) When I make the changes, you code executes without error. Regards, Chris ------------------------------------------------------------------------------ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2015-09-01 19:22:58
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On 9/1/2015 2:05 PM, Edward Vidal wrote: > Still not getting the status to go green in my co-simulation.I just > push my latest code to github.Thanks Regards What "green light" status are you talking about? Are you talking about travis-ci status? Or do simply mean the test completes successfully? Regards, Chris |
From: Edward V. <dev...@sb...> - 2015-09-01 21:17:07
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Chris, The output signal status is the output of the module dut_test which is in the file "ifchains.v". I can see that signal a in tb_ifchain1 changes from 0 to 12 & signal b in tb_ifchain1 changes from 0 to 2 at time 100 ns. Just before the 100 ns. I see signal rstn in both tb_ifchain1 & dut_test go high to lo on the positive transition of the clk in both tb_ifchain1 & dut_test. While the signal status in both tb_ifchain1 & dut_test is always red. Also the signals a & b are yellow in dut_test and green in tb_ifchain. Should this be normal, since the signals a & b are only used in dut_test? I am thinking, not sure, that upper 2 bits of signal a 1100 and the 2nd bit of signal b 0010 should result in the status going to 1 in dut_test. This would be green in the gtkwave figure. Instead I always see a red signal. I get the same results on the Raspberry Pi as on the PC. On the PC I am using a different myhdl.vpi which changes the ifchain file at runtime. My errors now must be how I am setting the values in the file tb_ifchains.v. Let me if I can provide any other information. thanks in advance. Regards Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, September 1, 2015 1:23 PM, Christopher Felton <chr...@gm...> wrote: On 9/1/2015 2:05 PM, Edward Vidal wrote: > Still not getting the status to go green in my co-simulation.I just > push my latest code to github.Thanks Regards What "green light" status are you talking about? Are you talking about travis-ci status? Or do simply mean the test completes successfully? Regards, Chris ------------------------------------------------------------------------------ _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |