Hi,
I'm not sure why the following code gives the conversion error mentioned
above.
===
from myhdl import *
class TlpTxInterface:
""" PCIe endpoint TX-interface """
def __init__(self):
self.tvalid = Signal(bool(False))
def tx_engine(clk, rst, tlp_tx):
t_tx_state = enum("TX_IDLE", "TX_CPLD_WORD0", "TX_CPLD_WORD1",
"TX_CPLD_WAIT_ACK", "TX_DONE")
s_tx_state_r = Signal(t_tx_state.TX_IDLE)
@always_seq(clk.posedge, reset=rst)
def logic():
if s_tx_state_r == t_tx_state.TX_IDLE:
s_tx_state_r.next = t_tx_state.TX_CPLD_WORD0
tlp_tx.tvalid.next = 0
elif s_tx_state_r == t_tx_state.TX_CPLD_WORD0:
tlp_tx.tvalid.next = 1
s_tx_state_r.next = t_tx_state.TX_CPLD_WORD1
elif s_tx_state_r == t_tx_state.TX_CPLD_WORD1:
tlp_tx.tvalid.next = 1
s_tx_state_r.next = t_tx_state.TX_CPLD_WAIT_ACK
elif s_tx_state_r == t_tx_state.TX_CPLD_WAIT_ACK:
s_tx_state_r.next = t_tx_state.TX_DONE
elif s_tx_state_r == t_tx_state.TX_DONE:
s_tx_state_r.next = t_tx_state.TX_CPLD_WORD1
return instances()
if __name__ == "__main__":
# Define port signals:
clk = Signal(bool(0))
rst = ResetSignal(0, active=1, async=False)
tlp_tx = TlpTxInterface()
# Convert to VHDL:
toVHDL.std_logic_ports = True
inst_tx_engine = toVHDL(tx_engine, clk, rst, tlp_tx)
===
Thanks,
Guy.
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