Thread: [myhdl-list] Tool to cosimulate VHDL in Vivado

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I've written a tool to do behavioural cosimulation of synchronous VHDL 
code using the Vivado simulator.

It's probably more accurately quasi-cosimulation as what it actually 
does is runs a MyHDL reference design and records all the inputs and the 
outputs at each clock cycle, then runs a device under test inside Vivado 
through the tcl interface, playing back to it the recorded inputs. The 
tool then returns the resultant set of outputs from both simulations for 
comparison.

There is an equivalent tool for cosimulating myhdl models with other 
myhdl models, so in principle it should be a simple case of writing the 
test suite for myhdl development, then trivially switching the test 
function to use Vivado.

The real win of this approach is it opens up the facility of a free 
simulator in order to do behavioural verification of MyHDL models of 
encrypted IP (most of the IP that is now shipped with Vivado). It's 
still necessary to have the MyHDL model, but at least the loop is now 
closed.

I've also written a set of support functions for common things like 
clock generation and random input generation for use in this framework.

This email is really to see if there is interest in me packaging this up 
and releasing it. The code is written to be solid and it has a complete 
test bench.

I suspect that it can be easily modified to support Verilog, and I 
daresay much of the effort would be applicable to other simulators that 
are not VPI/VHPI compliant.

Cheers,

Henry