myhdl-list

[myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

I'm trying to do a poor man's RTL co-simulation by creating the files 
needed for simulation and the relevant stimulus files (from the MyHDL 
simulation), then writing the outputs from the Xilinx simulation to file 
for post-simulation comparison. For this I need a clock.

Consider:

def ClkDriver(clk, period=20):

     lowTime = int(period/2)
     highTime = period - lowTime

     @instance
     def driveClk():
         while True:
             yield delay(lowTime)
             clk.next = 1
             yield delay(highTime)
             clk.next = 0

     return driveClk

This is converted to the following (pertinent) VHDL:

architecture MyHDL of ClkDriver is

constant lowTime: integer := 10;
constant highTime: integer := 10;

begin

CLKDRIVER_DRIVECLK: process is
begin
     while True loop
         wait for lowTime ns;
         clk <= '1';
         wait for highTime ns;
         clk <= '0';
     end loop;
     wait;
end process CLKDRIVER_DRIVECLK;

end architecture MyHDL;

Xilinx Vivado complains this is a syntax error. It doesn't like the use 
of a constant in the "wait for lowTime ns", though it's easily fixed 
with e.g. "wait for 10 ns".

Is this Vivado being crap, or is this expected behaviour? I could always 
create my own custom VHDL template, but it would be neater to have MyHDL 
do it for me.

Many thanks,

Henry

Re: [myhdl-list] delays in VHDL conversion

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> I'm trying to do a poor man's RTL co-simulation by creating the files 
> needed for simulation and the relevant stimulus files (from the MyHDL 
> simulation), then writing the outputs from the Xilinx simulation to 
file 
> for post-simulation comparison. For this I need a clock.
> 
> Consider:
> 
> def ClkDriver(clk, period=20):
> 
>      lowTime = int(period/2)
>      highTime = period - lowTime
> 
>       <at> instance
>      def driveClk():
>          while True:
>              yield delay(lowTime)
>              clk.next = 1
>              yield delay(highTime)
>              clk.next = 0
> 
>      return driveClk
> 
> This is converted to the following (pertinent) VHDL:
> 
> architecture MyHDL of ClkDriver is
> 
> constant lowTime: integer := 10;
> constant highTime: integer := 10;
> 
> begin
> 
> CLKDRIVER_DRIVECLK: process is
> begin
>      while True loop
>          wait for lowTime ns;
>          clk <= '1';
>          wait for highTime ns;
>          clk <= '0';
>      end loop;
>      wait;
> end process CLKDRIVER_DRIVECLK;
> 
> end architecture MyHDL;
> 
> Xilinx Vivado complains this is a syntax error. It doesn't like the 
use 
> of a constant in the "wait for lowTime ns", though it's easily fixed 
> with e.g. "wait for 10 ns".
> 
> Is this Vivado being crap, or is this expected behaviour? I could 
always 
> create my own custom VHDL template, but it would be neater to have 
MyHDL 
> do it for me.
> 
> <snip>

Actually the converted code is wrong, the statements like:
    constant lowTime: integer := 10;
    wait for lowTime ns;

are incorrect, they should either be:
    constant lowTime: integer := 10;
    wait for lowTime * 1.0 ns;

or:
    constant lowTime: time := 10.0 ns;
    wait for lowTime ;

Should be easy to fix in the MyHDL code.

Regards,

Josy
 

Re: [myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

On 08/02/15 22:22, Josy Boelen wrote:
<snip>
> Actually the converted code is wrong, the statements like:
>      constant lowTime: integer := 10;
>      wait for lowTime ns;
>
> are incorrect, they should either be:
>      constant lowTime: integer := 10;
>      wait for lowTime * 1.0 ns;
>
> or:
>      constant lowTime: time := 10.0 ns;
>      wait for lowTime ;
>
> Should be easy to fix in the MyHDL code.

You mean in the conversion routines? The easiest way I can think of is 
to replace the "ns" string with "* 1.0 ns"
here:
https://bitbucket.org/jandecaluwe/myhdl/src/b07b52398020b3bd737d0b4f1574f0d94eefccb5/myhdl/conversion/_toVHDL.py?at=default#cl-970

No doubt that will break other things though? Is there a reason why 
there can't always be a multiplier (other than code neatness)?

Henry

Re: [myhdl-list] delays in VHDL conversion

[Josy B. <jos...@gm...>]

Henry Gomersall <heng <at> cantab.net> writes:

> 
> On 08/02/15 22:22, Josy Boelen wrote:
> <snip>
> > Actually the converted code is wrong, the statements like:
> >      constant lowTime: integer := 10;
> >      wait for lowTime ns;
> >
> > are incorrect, they should either be:
> >      constant lowTime: integer := 10;
> >      wait for lowTime * 1.0 ns;
> >
> > or:
> >      constant lowTime: time := 10.0 ns;
> >      wait for lowTime ;
> >
> > Should be easy to fix in the MyHDL code.
> 
> You mean in the conversion routines? The easiest way I can think of is 
> to replace the "ns" string with "* 1.0 ns"
> here:
> 
https://bitbucket.org/jandecaluwe/myhdl/src/b07b52398020b3bd737d0b4f1574
f0d94eefccb5/myhdl/conversion/_toVHDL.py?at=default#cl-970
> 
> No doubt that will break other things though? Is there a reason why 
> there can't always be a multiplier (other than code neatness)?
> <snip>

I meant exactly that, and the '* 1.0 ns' would be my preferred too, and 
is definitely the easiest. I don't think this will break any other code.

Specifically setting the 'times' using real numbers, e.g.:
  def ClkDriver(clk, period=20.0):

     lowTime = period / 2
     highTime = period - lowTime
     ...
     wait for lowTime ns;

will not help either, as VHDL expects a time-type value and the 'ns' is 
part of that and can not be used as a units specifier. I'm not aware if 
there is a cast to convert something (int or real) into a time-type. Of 
course we could write the function(s) to do this and add these to the 
MyHDL package and modify the MyHDL code:
 elif f is delay:
            self.write( "to_VHDLtime( ")
            self.visit(node.args[0])  # this will end up in visit_Num() 
and produce an integer or a real (I suppose)
            self.write(" )")
            return

Regards,

Josy

Re: [myhdl-list] delays in VHDL conversion

[Henry G. <he...@ca...>]

On 09/02/15 08:38, Josy Boelen wrote:
<snip>
> I'm not aware if
> there is a cast to convert something (int or real) into a time-type. Of
> course we could write the function(s) to do this and add these to the
> MyHDL package and modify the MyHDL code:
>   elif f is delay:
>              self.write( "to_VHDLtime( ")
>              self.visit(node.args[0])  # this will end up in visit_Num()
> and produce an integer or a real (I suppose)
>              self.write(" )")
>              return

That's quite a neat method. It has the advantage of being explicit and 
clear in the resultant VHDL.

Are the constants new in 0.9? Presumably there should be a test for this...

Henry

Re: [myhdl-list] delays misconverted in VHDL conversion

[Henry G. <he...@ca...>]

On 08/02/15 22:22, Josy Boelen wrote:
> Henry Gomersall <heng <at> cantab.net> writes:
>
>> >
>> >I'm trying to do a poor man's RTL co-simulation by creating the files
>> >needed for simulation and the relevant stimulus files (from the MyHDL
>> >simulation), then writing the outputs from the Xilinx simulation to
> file
>> >for post-simulation comparison. For this I need a clock.
>> >
>> >Consider:
>> >
>> >def ClkDriver(clk, period=20):
>> >
>> >      lowTime = int(period/2)
>> >      highTime = period - lowTime
>> >
>> >       <at> instance
>> >      def driveClk():
>> >          while True:
>> >              yield delay(lowTime)
>> >              clk.next = 1
>> >              yield delay(highTime)
>> >              clk.next = 0
>> >
>> >      return driveClk
>> >
>> >This is converted to the following (pertinent) VHDL:
>> >
>> >architecture MyHDL of ClkDriver is
>> >
>> >constant lowTime: integer := 10;
>> >constant highTime: integer := 10;
>> >
>> >begin
>> >
>> >CLKDRIVER_DRIVECLK: process is
>> >begin
>> >      while True loop
>> >          wait for lowTime ns;
>> >          clk <= '1';
>> >          wait for highTime ns;
>> >          clk <= '0';
>> >      end loop;
>> >      wait;
>> >end process CLKDRIVER_DRIVECLK;
>> >
>> >end architecture MyHDL;
>> >
>> >Xilinx Vivado complains this is a syntax error. It doesn't like the
> use
>> >of a constant in the "wait for lowTime ns", though it's easily fixed
>> >with e.g. "wait for 10 ns".
>> >
>> >Is this Vivado being crap, or is this expected behaviour? I could
> always
>> >create my own custom VHDL template, but it would be neater to have
> MyHDL
>> >do it for me.
>> >
>> ><snip>
> Actually the converted code is wrong, the statements like:
>      constant lowTime: integer := 10;
>      wait for lowTime ns;
>
> are incorrect, they should either be:
>      constant lowTime: integer := 10;
>      wait for lowTime * 1.0 ns;
>
> or:
>      constant lowTime: time := 10.0 ns;
>      wait for lowTime ;
>
> Should be easy to fix in the MyHDL code.

Can anyone else comment on whether this wants to be fixed? Happy to 
raise a PR with some form of a fix. I feel this could easily go into 0.9.

My reading of the spec suggests the ns is an integral part of the time 
type, not some general numerical attribute, so I think the failure is 
expected.

Cheers,

Henry

Re: [myhdl-list] delays misconverted in VHDL conversion

[Christopher F. <chr...@gm...>]

<snip>
>> Actually the converted code is wrong, the statements like:
>>       constant lowTime: integer := 10;
>>       wait for lowTime ns;
>>
>> are incorrect, they should either be:
>>       constant lowTime: integer := 10;
>>       wait for lowTime * 1.0 ns;
>>
>> or:
>>       constant lowTime: time := 10.0 ns;
>>       wait for lowTime ;
>>
>> Should be easy to fix in the MyHDL code.
>
> Can anyone else comment on whether this wants to be fixed? Happy to
> raise a PR with some form of a fix. I feel this could easily go into 0.9.
>
> My reading of the spec suggests the ns is an integral part of the time
> type, not some general numerical attribute, so I think the failure is
> expected.

It sounds like something that should be fixed, I don't recall
(without taking the time to look it up) the exact VHDL policy
but Joys' and your explanation sounds correct.

I would create an issue [1] and include the complete example (the
small conversion snippet) and include the warning.  With Modelsim
a similar error is thrown.

     $ vcom pck_myhdl_09.vhd clock_driver.vhd
     Model Technology ModelSim ALTERA vcom 10.1e
     Compiler 2013.06 Jun 12 2013
     -- Loading package STANDARD
     -- Loading package TEXTIO
     -- Loading package std_logic_1164
     -- Loading package NUMERIC_STD
     -- Compiling package pck_myhdl_09
     -- Compiling package body pck_myhdl_09
     -- Loading package pck_myhdl_09
     -- Loading package pck_myhdl_09
     -- Compiling entity clock_driver
     -- Compiling architecture MyHDL of clock_driver
     ** Error: clock_driver.vhd(38): near "ns": expecting ';'
     ** Error: clock_driver.vhd(44): VHDL Compiler exiting


After the issue has been created, if you have a fix, created a PR
and someone will decide if it should be part of 0.9 or a later
bug fix release.

And note, Jan has created a nice outline how to contribute to the
project [2].

Regards,
Chris

[1] https://bitbucket.org/jandecaluwe/myhdl/issues?status=new&status=open
[2] http://dev.myhdl.org/guide.html