myhdl-list

[myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello All,

I am using the following python code to generate my Verilog and VHDL files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.py
The files get created which are the following two files
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhd
and https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v

The VHDL file when I try to synthesize I get the error
"Use <= to assign to signal res_out_x".  Changing the 4 lines where ":=:" appears to "<="
res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - (shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 1)));
Process "Synthesize - XST" completed successfully
My entity are all inputs. How do you access the output?
entity jp_process is
    port (
        sig_in_x_i: in unsigned(15 downto 0);
        res_out_x_i: in unsigned(15 downto 0);
        left_s_i: in unsigned(15 downto 0);
        sam_s_i: in unsigned(15 downto 0);
        right_s_i: in unsigned(15 downto 0);
        flgs_s_i: in unsigned(9 downto 0)
    );
end entity jp_process;

The Verilog file has no problem with the Synthesize.  I generated a Test Bed
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.v
I am not able to see get the output signal
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIF
Any and all help is appreciated.
Thanks


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am using the following python code to generate my Verilog 
and VHDL fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.pyThe files get created 
which are the following two fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhdand 
https://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vThe V
>  HDL file when I try to synthesize I get the error"Use <= to assign to 
signal res_out_x".  Changing the 4 lines where ":=:" appears to
>  "<="res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - 
(shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 
1)));Process "Synthesize - XST" completed successfullyMentity jp_process 
is    port (        sig_in_x_i: in unsigned(15 downto 0);        
res_out_x_i: in unsigned(15 downto 0);        left_s_i: in unsigned(15 
downto 0);        sam_s_i: in unsigned(15 downto 0);        right_s_i: 
in unsigned(15 downto 0);        flgs_s_i:
>  in unsigned(9 downto 0)    );end entity jp_process;The Verilog file 
has no problem with the Synthesize.  I generated a Test 
Bedhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.vI am not able to see 
get the output signalhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIFAny and all help is 
appreciated.Thanks
>  <snip>
>My entity are all inputs. How do you access the output?

What'd you expect? If you don't declare outputs, you just don't have 
any. MyHDL gets mixed up between variables and signals, but I wouldn't 
blame MyHDL for that. That the Verilog converted code synthesizes is 
just a fluke (I guess to do with blocking and non-blocking?). If you let 
ISE go all the way, you very probably end up with  everything optimised 
away.
Our BDFL would say, simulate first then convert ... After all, one of 
the greatest features of MyHDL is in Simulation

Regards,

Josy

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello Josy,
I thought that items on left were outputs and items on the right were inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
I just wanted signals that  were arrays.   Since these are, I assuming shadow signals that is why I am not getting any output.  This is a new topic for me and I have not worked with shadow signals before.  What must I do to get the res_out_x or res_out_x_i to be and output?   This must be a really bad question.  I do appreciate all the help.


Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 7:44 AM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello All,I am using the following python code to generate my Verilog 
and VHDL fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/array_jpeg.pyThe files get created 
which are the following two fileshttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vhdand 
https://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/jp_process.vThe V
>  HDL file when I try to synthesize I get the error"Use <= to assign to 
signal res_out_x".  Changing the 4 lines where ":=:" appears to
>  "<="res_out_x((LVL0 - 1)) := (sam_s((LVL0 - 1)) - 
(shift_right(left_s((LVL0 - 1)), 1) + shift_right(right_s((LVL0 - 1)), 
1)));Process "Synthesize - XST" completed successfullyMentity jp_process 
is    port (        sig_in_x_i: in unsigned(15 downto 0);        
res_out_x_i: in unsigned(15 downto 0);        left_s_i: in unsigned(15 
downto 0);        sam_s_i: in unsigned(15 downto 0);        right_s_i: 
in unsigned(15 downto 0);        flgs_s_i:
>  in unsigned(9 downto 0)    );end entity jp_process;The Verilog file 
has no problem with the Synthesize.  I generated a Test 
Bedhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/TBjp_process.vI am not able to see 
get the output signalhttps://github.com/develone/jpeg-2000-
test/blob/master/jpeg2k/parallel_jpeg/nooutput.GIFAny and all help is 
appreciated.Thanks
>  <snip>
>My entity are all inputs. How do you access the output?

What'd you expect? If you don't declare outputs, you just don't have 
any. MyHDL gets mixed up between variables and signals, but I wouldn't 
blame MyHDL for that. That the Verilog converted code synthesizes is 
just a fluke (I guess to do with blocking and non-blocking?). If you let 
ISE go all the way, you very probably end up with  everything optimised 
away.
Our BDFL would say, simulate first then convert ... After all, one of 
the greatest features of MyHDL is in Simulation

Regards,

Josy



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Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Josy B. <jos...@gm...>]

Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello Josy,
> 
> I thought that items on left were outputs and items on the right were 
inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
> 
> I just wanted signals that  were arrays.   Since these are, I assuming 
shadow signals that is why I am not getting any output.  This is a new 
topic for me and I have not worked with shadow signals before.  What 
must I do to get the res_out_x or res_out_x_i to be and output?   This 
must be a really bad question.  I do appreciate all the help.
> 
> <snip>

Edward,

I think that most of your intentions, arrays and shadow signals worked 
OK. 
You have to specifically name  the output signals in the function 
declaration:
  def jp_process(sig_in_x_i, left_s_i, sam_s_i, right_s_i,flgs_s_i, 
*res_out_x*, W0=3, LVL0=4, W1=3, LVL1=4, W2=3, LVL2=4,  W3=3, LVL3=4 ):

and declare *res_out_x* before calling the function. I did remove the 
unused input signal *res_out_x_i*.

Now you are 'slicing' 1D input vectors into 1D*1D vectors (which works 
fine, it seems). So if the res_out_x is also a 1D vector, you still have 
to declare an internal 1D*1D signal and concatenate this one to a 1D 
output vector. Something like:
 lres_out_x = [Signal(intbv()[xx:]) for _ in range(Y)]

and later add an always_comb function to assemble the output vector
@always_comb
def assignouts():
    for i in range(Y):
        res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]


It would be nice if we can extend MyHDL to do these mappings/assignments 
with less typing. 

Re-using the *res_out_x_i* as an output would be a possibility, but will 
the become an 'inout' signals, which is a very bad idea (except for the 
truly bidirectional top-level pins of the FPGA)

Regards,

JOsy

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Edward V. <dev...@sb...>]

Hello all,
Thanks to Josy Boelen for getting me this far.

When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?

My code  is located at

https://github.com/develone/jpeg-2000-test/tree/master/jpeg2k/parallel_jpeg

array_jpeg.py, jpeg_constants.py, jp_process.v, and jp_process.vhd.
These 4 arrays are going to be on the order of 8192 bits wide for 3 arrays and 1 of 5120 bits wide. 

What method would you recommend for setting the values of these arrays 4 ram or 4 fifo instances?  

How do you determine which takes more resources?
Thanks, I do appreciate all the help.
  


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613


On Sunday, February 8, 2015 2:12 PM, Josy Boelen <jos...@gm...> wrote:
 


Edward Vidal <develone <at> sbcglobal.net> writes:

> 
> 
> Hello Josy,
> 
> I thought that items on left were outputs and items on the right were 
inputs.  I was trying to follow an example  posted  Raman Muthukishnan.
> 
> I just wanted signals that  were arrays.   Since these are, I assuming 
shadow signals that is why I am not getting any output.  This is a new 
topic
 for me and I have not worked with shadow signals before.  What 
must I do to get the res_out_x or res_out_x_i to be and output?   This 
must be a really bad question.  I do appreciate all the help.
> 
> <snip>

Edward,

I think that most of your intentions, arrays and shadow signals worked 
OK. 
You have to specifically name  the output signals in the function 
declaration:
  def jp_process(sig_in_x_i, left_s_i, sam_s_i, right_s_i,flgs_s_i, 
*res_out_x*, W0=3, LVL0=4, W1=3, LVL1=4, W2=3, LVL2=4,  W3=3, LVL3=4 ):

and declare *res_out_x* before calling the function. I did remove the 
unused input signal *res_out_x_i*.

Now you are 'slicing' 1D input vectors into 1D*1D vectors (which works 
fine, it seems). So if the res_out_x is also a 1D vector, you still have 
to declare an internal 1D*1D signal and concatenate this one to a 1D 
output vector. Something like:
lres_out_x = [Signal(intbv()[xx:]) for _ in range(Y)]

and later add an always_comb function to assemble the output vector
@always_comb
def assignouts():
    for i in range(Y):
        res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]


It would be nice if we can extend MyHDL to do these mappings/assignments 
with less typing. 

Re-using the *res_out_x_i* as an output would be a possibility, but will 
the become an 'inout' signals, which is a very bad idea (except for the 
truly bidirectional top-level pins of the FPGA)

Regards,

JOsy
------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
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Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

On 2/9/2015 10:50 AM, Edward Vidal wrote:
> Hello all,
> Thanks to Josy Boelen for getting me this far.
>
> When using arrays,  the output signal or signals, need to be created before the calling the method that creates the arrays and  @always_comb.
> How would you pass a list of signed signals? Or do they need to be signed base on the information provided by Chris Felton.?
>

Let's back up a little bit.  List of Signals (array) is
often used to represent RAM/ROM but it is also used to
logically organize signals [1][2].  If you happen to have
a very large bus you might want to break it down into
smaller logical components.  I am going to call the arrays
list-of-signals (LoS) here.

Couple things to note, LoS cannot be used as final port
interface.  In other words, you cannot convert a LoS as
a top-level port.  In a design LoS can be passed between
modules because the design is flattened.  For an actual
design it is rare that you will have a very large bus
off-chip, in the cases that you do you will need to create
mapping (like Joys example) to flatten the bus.

At this point I don't know what you are trying to achieve,
it is often difficult (i.e. takes time) to figure out your
code just from the source.  As mentioned before, simple
examples of what you are trying to achieve would help.

Here is a simple example.  I want to take a LoS (array)
of some arbitrary size and subtract some constant value
and assign it to a new LoS as the same size of the LoS
passed.

     x = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]
     y = [Signal(intbv(0, min=-88, max=88)
          for _ in range(N)]

     def m_los_subtractor(x, y, A=7):
         N = len(x)
         @always_comb
         def rtl():
             for ii in range(N):
                 y[ii].next = x - A
         return rtl

If the above module is used in a design it should work
(disclaimer I didn't debug, there could be a typo).  An
LoS is passed that will hold the values and an LoS that
is passed will be filled with the result.  Also note,
this example is incomplete because it assumes *x* will
always be min+A.

If you are trying to convert module by module and using
LoS as ports, this will be difficult because you will have
to constantly be translating between the large flat bus
and an LoS.

I don't know if ShadowSignals are what you really want,
I would do like Joys example (I think that is what he was
doing) and map between a wide bus and an LoS and not use
ShadowSignals.

Hope this helps,
Chris

[1] 
http://docs.myhdl.org/en/latest/whatsnew/0.6.html#conversion-of-lists-of-signals
[2] 
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference 

Re: [myhdl-list] All inputs no output with generated Verilog and VHDL

[Christopher F. <chr...@gm...>]

<snip>
>
> and later add an always_comb function to assemble the output vector
> @always_comb
> def assignouts():
>      for i in range(Y):
>          res_out_x.next[ (i+1)*xx:i*xx] = lres_out_x[i]
>
>
> It would be nice if we can extend MyHDL to do these mappings/assignments
> with less typing.
>

This has come up in a couple threads (not this exact
topic but similar LoS/array things).  I think someone
will need to take some time and think through LoS/arrays.

We have a tricky task, we want to be able to do what the
current HDLs do but we don't want to use the current HDLs
as the benchmark :)  Meaning, we don't want to simply do
something because V* does it.  Things like multi-dimension
array/LoS could use some thought.  What is supported, what
is not, what are the limitations, is it only conversion,
etc.  When we did this exercise with interfaces we discovered
some nice tricks that you could do outside the myhdl
generators.

Regards,
Chris