Thread: [myhdl-list] ISE 14.7 and FSM

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Hello All,
Fairly new to both VHDL and myhdl.
I would appreciate any and all help. Thanks in advance.
I have created other FSM that I used in simulation and it worked okay.
I am using ISE 14.7 for a Spartan6 XC6SLX9.
If I can provide any additional information just let me know.
Creating a project with xess_jpeg_top.vhd & pck_myhdl_09.vhd will synthesize okay.
The file xess_jpeg_top.vhd is not a package and has the following RTL modules.

XESS_JPEG_TOP_INSTANCE_2_MUXLOGIC
XESS_JPEG_TOP_INSTANCE_3_JPEG
XESS_JPEG_TOP_INSTANCE_4_SDRAM_RD
XESS_JPEG_TOP_INSTANCE_5_RAM2SIG
XESS_JPEG_TOP_INSTANCE_7_FSMUPDATE

Adding a FSM module see below.
XESS_JPEG_TOP_INSTANCE_6_FSM to the xess_jpeg_top.vhd now creates a package.
When I try to synthesize generates the following errors.
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 172: Syntax error near "case".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 176: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 180: Syntax error near "end".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 184: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 187: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 190: Syntax error near "when".
ERROR:HDLCompiler:806 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 193: Syntax error near "end".
ERROR:HDLCompiler:854 - "C:\Users\vidal\Documents\GitHub\jpeg-2000-test\jpeg2k\XESS_SdramSPInst\xess_jpeg_top.vhd" Line 61: Unit <myhdl> ignored due to previous errors.
Lines 169-194
XESS_JPEG_TOP_INSTANCE_6_FSM: process (addr_r, state, even_odd_x) is
begin
    (even_odd_x <= '0')
    case state is
        when INIT =>
            addr_x <= to_unsigned(1, 24);
            (state <= ODD_SAMPLES)
        when ODD_SAMPLES =>
            if (addr_r = 1) then
                addr_x <= to_unsigned(2, 24);
                (state <= EVEN_SAMPLES)
            end if;
        when EVEN_SAMPLES =>
            addr_x <= to_unsigned(2, 24);
            (state <= WR_DATA)
        when WR_DATA =>
            addr_x <= to_unsigned(8, 24);
            (state <= INTERLACE)
        when INTERLACE =>
            addr_x <= to_unsigned(16, 24);
            (state <= DONE)
        when others => -- DONE
            addr_x <= to_unsigned(1, 24);
            (state <= INIT)
    end case;
end process XESS_JPEG_TOP_INSTANCE_6_FSM;
The file that I am using to generate the FSM is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg2k/XESS_SdramSPInst/xess_jpeg_top.vhd
The following is the checked message.
trying to add a FSM
when following 4 lines are un-commented 
def xess_jpeg_top(clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s, state, even_odd_r, even_odd_x):
instance_6 = RamCtrl(addr_r, addr_x, state, even_odd_r, even_odd_x)
return instance_2, instance_3, instance_4, instance_5, instance_6, instance_7
toVHDL(xess_jpeg_top, clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s, state, even_odd_r, even_odd_x)
the xess_jpeg_top.vhd now creates a package.

when the following 3 lines are un-commented and the line instance_6 = RamCtrl(addr_r, addr_x, state, even_odd_r, even_odd_x) is commented out
def xess_jpeg_top(clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s):
return instance_2, instance_3, instance_4, instance_5, instance_7
toVHDL(xess_jpeg_top, clk_fast, addr_r, addr_x, addr_r1, addr_r2, muxsel, dataToRam_r, dataToRam_x, sig_in, noupdate_s, res_s, jp_lf, jp_sa ,jp_rh, jp_flgs, reset_col, rdy, addr_not_reached, offset, dataFromRam_s)
The XESS_JPEG_TOP_INSTANCE_6_FSM is not generated and the file xess_jpeg_top.vhd is not a package.
Thanks,

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613