myhdl-list

[myhdl-list] Using existing HDL modules

[Mike G. <mj...@gi...>]

Hi

How do you access chip primitives and hard IP blocks in MyHDL? The chip
vendor supplies modules and instantiation templates in Verilog or VHDL. Is
there any way of including or importing these without having to edit the
Verilog or VHDL file generated by MyHDL? I can't work out whether the
user-defined code facility can do this.

My knowledge of Verilog and VHDL is very limited.

Many thanks

Mike

Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 8:59 AM, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>

In short, user-defined code is used to instantiate
third party IP provided in Verilog of VHDL (including
hard IP).  For simulation you will need to created
a functional model or co-simulate with existing V*
models.

http://docs.myhdl.org/en/latest/manual/conversion.html#user-defined-code

Regards,
Chris

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 03/11/14 17:11, Christopher Felton wrote:
> co-simulate with existing V*
> models.

The potential problem with this being the paranoid encryption that seems 
to be de rigueur among IP authors. This is an issue if you want to use 
Icarus verilog, but Aldec and Modelsim should be ok.

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Guy E. <guy...@gm...>]

Hello Mike,

I have an example showing how to instantiate an IBUFDS component from the
Xilinx Unisim library with user-defined code. You'll find it on the slide
number 43 of my presentation on "FPGA Design with Python and MyHDL" (
http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python
).

Hope this helps,
Guy.


Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no... <Guy...@gm...>
Follow me on Twitter: @geschema <http://twitter.com/geschema>
Skype: guy.eschemann
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

On Mon, Nov 3, 2014 at 3:59 PM, Mike Gill <mj...@gi...> wrote:

> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
>
> My knowledge of Verilog and VHDL is very limited.
>
> Many thanks
>
> Mike
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 03/11/14 17:52, Guy Eschemann wrote:
> I have an example showing how to instantiate an IBUFDS component from 
> the Xilinx Unisim library with user-defined code. You'll find it on 
> the slide number 43 of my presentation on "FPGA Design with Python and 
> MyHDL" 
> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).

Hi Guy, that's a great presentation.

One question though: you say on page 45 that MyHDL cannot generate 
parameterizable HDL. What do you mean by this?

My understanding is that with the flexibility of python, parameterizable 
HDL (or indeed almost any kind of metaprogramming niceness) is a 
wonderful thing to be doing with MyHDL. Have I missed something?

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Christopher F. <chr...@gm...>]

On 11/3/2014 12:04 PM, Henry Gomersall wrote:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
>
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>

The HDL in Python (the MyHDL) is very parameterizable,
modular, scalable, etc.  But the generated Verilog/VHDL
is not.  The generated Verilog/VHDL is an convenient
intermediate format.

Hope that helps,
Chris

Re: [myhdl-list] Using existing HDL modules

[Guy E. <gu...@no...>]

Hello Henry,

what this means is that you cannot generate VHDL code that is 
parameterizable using VHDL generics (think of a FIFO that has a "depth" 
generic for example). The parametrization has to be done in MyHDL before 
the actual VHDL code is generated.

As far as I know, this limitation applies to all all high-level design 
solutions (C-based HLS, Bluespec SV, etc.). It may or may not be an 
issue for you.

Regards,
Guy.

Am 03.11.2014 19:04, schrieb Henry Gomersall:
> On 03/11/14 17:52, Guy Eschemann wrote:
>> I have an example showing how to instantiate an IBUFDS component from
>> the Xilinx Unisim library with user-defined code. You'll find it on
>> the slide number 43 of my presentation on "FPGA Design with Python and
>> MyHDL"
>> (http://www.slideshare.net/GuyEschemann/2014-all-programmabe-days-fpga-design-with-python).
> Hi Guy, that's a great presentation.
>
> One question though: you say on page 45 that MyHDL cannot generate
> parameterizable HDL. What do you mean by this?
>
> My understanding is that with the flexibility of python, parameterizable
> HDL (or indeed almost any kind of metaprogramming niceness) is a
> wonderful thing to be doing with MyHDL. Have I missed something?
>
> Cheers,
>
> Henry
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

-- 
Guy Eschemann
FPGA Consultant, CEO
noasic GmbH
Auenheimer Str. 26a
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
Follow me on Twitter: @geschema
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

Re: [myhdl-list] Using existing HDL modules

[Henry G. <he...@ca...>]

On 04/11/14 07:42, Guy Eschemann wrote:
> what this means is that you cannot generate VHDL code that is
> parameterizable using VHDL generics (think of a FIFO that has a "depth"
> generic for example). The parametrization has to be done in MyHDL before
> the actual VHDL code is generated.
Oh, I understand - so you mean you can't pass around a parameterizable 
v* block for others to use. Not as problematic as I interpreted your 
point as being. :)

Cheers,

Henry

Re: [myhdl-list] Using existing HDL modules

[Jan C. <jen...@mu...>]

On 03/11/14 14:59, Mike Gill wrote:
> Hi
>
> How do you access chip primitives and hard IP blocks in MyHDL? The chip
> vendor supplies modules and instantiation templates in Verilog or VHDL. Is
> there any way of including or importing these without having to edit the
> Verilog or VHDL file generated by MyHDL? I can't work out whether the
> user-defined code facility can do this.
I have a MyHDL RAM (model?) with content initialisation code which 
simulates in MyHDL and is accepted by the Lattice (Ex Silicon Blue) 
toolchain.

This puts the RAM image into Verilog defparam statements in MyHDL 
user-defined code for the synth tools, and initialises the MyHDL 
RAM model for simulation.

AFAICT the same technique will allow direct access to the all of 
chip primitives.   Haven't looked at IP blocks.

Let me know if you'd like me to send or post code.

Jan Combs.