On 5/3/2014 3:14 AM, Josy Boelen wrote:
> Guy Eschemann <guy <at> noasic.com> writes:
>
> I experimented a bit with your code and got the intended result when
> replacing 'inc_comb.vhdl_code' with 'top.vhdl_code'. Now you wrapped
> 'inc_comb' inside a 'top' module which is the one you convert, so this may
> make sense?
>
> Regards,
>
> Josy
>
Yes, the generators (see [1] for intro on generators)
cannot have the user-defined code attribute only a
module (a function).
Typically, in MyHDL we call a (myhdl) module a Python
function that returns MyHDL generators (yes this overlaps
with the Python definition of a module, context specific
(i.e. a file)).
As Josy, replied, if you modify the code to (sorry changed
some of the signal names, see below)
Regards,
Chris
[1]
http://docs.myhdl.org/en/latest/manual/background.html#a-small-tutorial-on-generators
#---------------------------------------------------------------
def m_top(clock, reset, x, y):
incx = Signal(y.val)
g = m_next_count(x, incx, 8)
@always_seq(clock.posedge, reset=reset)
def rtl():
y.next = incx
return g, rtl
def m_next_count(x, y, n):
@always(x)
def logic():
pass
y.driven = "wire"
return logic
m_next_count.vhdl_code = \
"""
$y <= ($x + 1) mod $n
"""
clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x,y = [Signal(intbv(0, min=-256, max=256)) for _ in range(2)]
toVHDL(m_top, clock, reset, x, y)
---------------------------------------------------------------
-- File: m_top.vhd
-- Generated by MyHDL 0.9dev
-- Date: Mon May 5 08:17:25 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_09.all;
entity m_top is
port (
clock: in std_logic;
reset: in std_logic;
x: in signed (8 downto 0);
y: out signed (8 downto 0)
);
end entity m_top;
architecture MyHDL of m_top is
signal incx: signed (8 downto 0);
begin
incx <= (x + 1) mod 8
M_TOP_RTL: process (clock, reset) is
begin
if (reset = '0') then
y <= to_signed(0, 9);
elsif rising_edge(clock) then
y <= incx;
end if;
end process M_TOP_RTL;
end architecture MyHDL;
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