myhdl-list

[myhdl-list] Connect internal signal to output port in MyHDL module

[Guy E. <gu...@no...>]

Hello,

I was wondering whether one of you MyHDL wizards would like to answer a 
question I posted on Stackoverflow: 
http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module

Thanks,
Guy.

-- 
Guy Eschemann
noasic e.K.
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77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
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Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

On 3/23/14 7:31 AM, Guy Eschemann wrote:
> Hello,
>
> I was wondering whether one of you MyHDL wizards would like to answer a
> question I posted on Stackoverflow:
> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>

This is a little odd - I don't believe you should
get an /inout/ if you use /o_count/ directly.

If it is the expected (I don't think it should be)
then there is a mismatch between the generated Verilog
and VHDL.

Here is my slightly modified version, using the
0.8 features.


     def m_counter(i_clk, i_reset, o_count):
         @always_seq(i_clk.posedge, reset=i_reset)
         def rtl_count():
             o_count.next = o_count + 1

     return rtl_count

     i_clk = Signal(bool(0))
     i_reset = ResetSignal(0, active=1, async=False)
     o_count = Signal(modbv(0, min=0, max=256))
     toVHDL(m_counter, i_clk, i_reset, o_count)
     toVerilog(m_counter, i_clk, i_reset, o_count)

full example here:
https://gist.github.com/cfelton/9725726
or try it out here http://www.edaplayground.com/x/3Aj
Note the example doesn't address the OT questions, it
shows the port mismatch between Verilog and VHDL.

The following is the generated port definitions for
VHDL and Verilog.  The /inout/ direction was only
generated in the VHDL?  This was generated with 0.8.1.

~~~[VHDL]~~~
     entity m_counter is
         port (
             i_clk: in std_logic;
             i_reset: in std_logic;
             o_count: inout unsigned(7 downto 0)
         );
     end entity m_counter;

~~~[Verilog]~~~
     module m_counter (
         i_clk,
         i_reset,
         o_count
     );
     input i_clk;
     input i_reset;
     output [7:0] o_count;
     reg [7:0] o_count;


If no one disagrees this is undesired, I can create
a bug ticket on bitbucket.

As for you question, I don't think there is an
alternative in the current release.

Regards,
Chris

Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

> full example here:
> https://gist.github.com/cfelton/9725726
> or try it out here http://www.edaplayground.com/x/3Aj
> Note the example doesn't address the OT questions, it
> shows the port mismatch between Verilog and VHDL.

Above it should be "OP's question" not "OT".

chris

Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Jan D. <ja...@ja...>]

On 03/23/2014 05:45 PM, Christopher Felton wrote:
> On 3/23/14 7:31 AM, Guy Eschemann wrote:
>> Hello,
>>
>> I was wondering whether one of you MyHDL wizards would like to answer a
>> question I posted on Stackoverflow:
>> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>>
>
> This is a little odd - I don't believe you should
> get an /inout/ if you use /o_count/ directly.

Yes you should, as per VHDL semantics. You can't read
an output port in VHDL, but you can in Verilog.

I answered on stack overflow.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Guy E. <gu...@no...>]

It looks like there are two aspects in this question, which can be 
addressed separately:

1. Directly incrementing "o_count" yields an inout port in the generated 
VHDL, but only when I convert this module stand-alone (which I did only 
for test purposes) -> that's OK for me.

2. Connecting an internal signal to an output port requires three lines 
of code in MyHDL:

    @always_comb
    def outputs():
         o_count.next = s_count

That's one of the rare cases where MyHDL seems to be more verbose than 
VHDL. In VHDL, this would be a one-liner:

    o_count <= std_logic_vector(s_count);

Regards,
Guy.

Am 24.03.2014 09:51, schrieb Jan Decaluwe:
> On 03/23/2014 05:45 PM, Christopher Felton wrote:
>> On 3/23/14 7:31 AM, Guy Eschemann wrote:
>>> Hello,
>>>
>>> I was wondering whether one of you MyHDL wizards would like to answer a
>>> question I posted on Stackoverflow:
>>> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>>>
>> This is a little odd - I don't believe you should
>> get an /inout/ if you use /o_count/ directly.
> Yes you should, as per VHDL semantics. You can't read
> an output port in VHDL, but you can in Verilog.
>
> I answered on stack overflow.
>
>

-- 
Guy Eschemann
noasic e.K.
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
Mobile: +49 (0) 173 72 51 886
gu...@no...
Follow me on Twitter: @geschema
http://noasic.com
http://fpga-news.de
USt-IdNr.: DE266749532
HRA 703582, Amtsgericht Freiburg i. Br.

Visit us at ALL PROGRAMMABLE PLC2 Days 2014
20-22.05.2014, Stuttgart, Germany

Re: [myhdl-list] Connect internal signal to output port in MyHDL module

[Christopher F. <chr...@gm...>]

On 3/24/14 3:51 AM, Jan Decaluwe wrote:
> On 03/23/2014 05:45 PM, Christopher Felton wrote:
>> On 3/23/14 7:31 AM, Guy Eschemann wrote:
>>> Hello,
>>>
>>> I was wondering whether one of you MyHDL wizards would like to answer a
>>> question I posted on Stackoverflow:
>>> http://stackoverflow.com/questions/22579122/connect-internal-signal-to-output-port-in-myhdl-module
>>>
>>
>> This is a little odd - I don't believe you should
>> get an /inout/ if you use /o_count/ directly.
>
> Yes you should, as per VHDL semantics. You can't read
> an output port in VHDL, but you can in Verilog.
>
> I answered on stack overflow.
>

Ah, that is right, thanks for the clarification
so many tidbits easily forgotten.

Regards,
Chris