myhdl-list

[myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Hi,

As I mentioned in a previous post, I´m using MyHDL to generate Verilog code 
directly from an ADC simulation program written in Python.

ADC´s can be generated with different number of stages and different 
resolutions per stage, so, my actual approach is based on the maximum number 
of ports that can be used, and if they aren´t used, they stay disconnected.

But this is not the perfect solution. Ports that are not used appear in final 
design, disconnected, but I need them to be discarded during conversion, to 
build a cleaner final design.

I can generate N different files to generate N different configurations, but 
it is certainly an ugly and heavy solution.

Is it possible to discard disconnected ports during conversion to Verilog?

Re: [myhdl-list] Dynamic ports

[Christopher F. <chr...@gm...>]

I would try something like the following - I have
not tested this thoroughly but something like this
should get you where you need to be.

In [116]: def m_top_vargs(**portmap):
      ...:     # need a method to locally reference all the
      ...:     # ports passed, example
      ...:     xcnt = sum([1 for k in portmap if 'x' in k])
      ...:     locallist = [Signal(intbv(0)[12:]) for _ in range(xcnt)]
      ...:     sel = portmap['sel']
      ...:     y = portmap['y']
      ...:     xi = 0
      ...:     for k,v in portmap.iteritems():
      ...:         if 'x' in k:
      ...:             locallist[ii].assign(v)
      ...:             xi += 1
      ...:     print(locallist)
      ...:

In [117]: portmap = {'sel': Signal(intbv(0)[4:]),'y': Signal(intbv(0)[21:])}
      ...: for ii in range(8):  # for the number of inputs
      ...:     portmap['x%d'%ii] = Signal(intbv(0)[21:])
      ...: m_top_vargs(**portmap)
      ...:
[Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)), 
Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)), 
Signal(intbv(0L)), Signal(intbv(0L))]


On 2/14/2014 9:57 AM, Carlos Silva wrote:
> Hi,
>
> As I mentioned in a previous post, I´m using MyHDL to generate Verilog code
> directly from an ADC simulation program written in Python.
>
> ADC´s can be generated with different number of stages and different
> resolutions per stage, so, my actual approach is based on the maximum number
> of ports that can be used, and if they aren´t used, they stay disconnected.
>
> But this is not the perfect solution. Ports that are not used appear in final
> design, disconnected, but I need them to be discarded during conversion, to
> build a cleaner final design.
>
> I can generate N different files to generate N different configurations, but
> it is certainly an ugly and heavy solution.
>
> Is it possible to discard disconnected ports during conversion to Verilog?
>
>
>
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> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
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>

Re: [myhdl-list] Dynamic ports

[Christopher F. <chr...@gm...>]

I am dazed and confused - my previous response is only
partial.  When your top-level function (myhdl module) is
evaluated the "ports" (function arguments) are determined.
In other-words, you do need to explicitly state them.

One method to work around (hack) is to create a string
and evaluate it, example:

     top_template = \
     """
     def m_outer_top(%s):
         portmap = {%s}
         return m_top_vargs(**portmap)
     """ % (", ".join(portmap.keys()),
            ", ".join(["'%s':%s"%(k,k) for k,v in portmap.items()]))

     exec(top_template)
     toVerilog(m_outer_top, *x, y=y, sel=sel)

If you dynamically build the "outer top" you can then use
the generic "inner top" and that might work.

Regards,
Chris

On 2/14/14 10:25 AM, Christopher Felton wrote:
> I would try something like the following - I have
> not tested this thoroughly but something like this
> should get you where you need to be.
>
> In [116]: def m_top_vargs(**portmap):
>        ...:     # need a method to locally reference all the
>        ...:     # ports passed, example
>        ...:     xcnt = sum([1 for k in portmap if 'x' in k])
>        ...:     locallist = [Signal(intbv(0)[12:]) for _ in range(xcnt)]
>        ...:     sel = portmap['sel']
>        ...:     y = portmap['y']
>        ...:     xi = 0
>        ...:     for k,v in portmap.iteritems():
>        ...:         if 'x' in k:
>        ...:             locallist[ii].assign(v)
>        ...:             xi += 1
>        ...:     print(locallist)
>        ...:
>
> In [117]: portmap = {'sel': Signal(intbv(0)[4:]),'y': Signal(intbv(0)[21:])}
>        ...: for ii in range(8):  # for the number of inputs
>        ...:     portmap['x%d'%ii] = Signal(intbv(0)[21:])
>        ...: m_top_vargs(**portmap)
>        ...:
> [Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)),
> Signal(intbv(0L)), Signal(intbv(0L)), Signal(intbv(0L)),
> Signal(intbv(0L)), Signal(intbv(0L))]
>
>
> On 2/14/2014 9:57 AM, Carlos Silva wrote:
>> Hi,
>>
>> As I mentioned in a previous post, I´m using MyHDL to generate Verilog code
>> directly from an ADC simulation program written in Python.
>>
>> ADC´s can be generated with different number of stages and different
>> resolutions per stage, so, my actual approach is based on the maximum number
>> of ports that can be used, and if they aren´t used, they stay disconnected.
>>
>> But this is not the perfect solution. Ports that are not used appear in final
>> design, disconnected, but I need them to be discarded during conversion, to
>> build a cleaner final design.
>>
>> I can generate N different files to generate N different configurations, but
>> it is certainly an ugly and heavy solution.
>>
>> Is it possible to discard disconnected ports during conversion to Verilog?
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Android apps run on BlackBerry 10
>> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
>> Now with support for Jelly Bean, Bluetooth, Mapview and more.
>> Get your Android app in front of a whole new audience.  Start now.
>> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Dynamic ports

[Carlos S. <car...@sa...>]

Yes, I confirm that the first method didn´t solve the problem (the design 
was built without ports, this time, as the ports were not recognized 
automatically by Verilog Converter).

I will try this second approach and give you feedback.

I also found another article posted by you:
http://www.fpgarelated.com/showarticle/544.php
That presents a new feature available in future MyHDL 0.9 version that seems 
to be a good solution to my problem. But I can´t wait for the new version of 
MyHDL.