myhdl-list

[myhdl-list] @always_comb - Conversion Error

[Carlos S. <car...@sa...>]

Hi,

I´ve had been using MyHDL to generate dynamic Verilog code directly from a 
python program. Leaving apart some natural difficulties due to my need of 
dynamic number of inputs and input widths, I´m facing a problem with an 
instance that I thought will be simple to implement, but returned me an 
unexpected error.

Im trying to implement a simple 8x3 multiplexer and I receive the following 
error:

Traceback (most recent call last):
  File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
    N_TRUNC, N_CALIB)
  File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line 
135, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line 
168, in _analyzeGens
    raise ConversionError(_error.UnsupportedType, n, info)
myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182: 
Object type is not supported in this context: in4

The related parts of my code are:

    n0 = Signal(intbv(15))[12:0]
    n1 = Signal(intbv(31))[12:0]
    n2 = Signal(intbv(63))[12:0]
    n3 = Signal(intbv(127))[12:0]
    n4 = Signal(intbv(255))[12:0]
    n5 = Signal(intbv(511))[12:0]
    n6 = Signal(intbv(1023))[12:0]
    n7 = Signal(intbv(2047))[12:0]
    db6 = Signal(intbv(0)[12:0])
    n = Signal(intbv(0)[3:0])
    U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)

# Multiplexer (8 inputs, 3 bits selector)
def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
    @always_comb
    def logic():
        if sel == 0x0:
            out.next = in0
        elif sel == 0x1:
            out.next = in1
        elif sel == 0x2:
            out.next = in2
        elif sel == 0x3:
            out.next = in3            
        elif sel == 0x4:
            out.next = in4          
        elif sel == 0x5:
            out.next = in5            
        elif sel == 0x6:
            out.next = in6
        else:
            out.next = in7      
    return instances()  


I have edited manually the code of "_extractHierarchy" with some print 
statements to obtain the types for each input, and it stops at in4, with the 
following sequence of prints:

<class 'myhdl._Signal._Signal'>
<class 'myhdl._Signal._Signal'>
<class 'myhdl._Signal._Signal'>
<class 'myhdl._Signal._Signal'>
<class 'myhdl._intbv.intbv'>


The original type of all the inputs is <class 'myhdl._intbv.intbv'>.

Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.


Any sugestions?

Re: [myhdl-list] @always_comb - Conversion Error

[Christopher F. <chr...@gm...>]

I didn't debug your example but the following is an
alternative approach.

A flexible mux:

     def m_mux(sigin, sigout, sel):
         @always_comb
         def rtl():
             sigout.next = sigin[sel]
         return rtl

A top-level wrapper (to convert) with the values you
previously provided:

     def m_mux_top(y, sel):
         # in this example, x has no drivers. make x constant
         x = (15, 31, 63, 127, 255, 511, 1023, 2047,)
         gmux = m_mux(x, y, sel)
         return gmux

When including the mux in a design, you can create
a list of signals and pass it to the mux.  The following
illustrates using the mux with a list of signals.  Note,
you have to jump through some hoops for conversion.  It
only makes sense to convert discrete top-level ports.  This
would not need to be completed (an intermediate list of
signals if top-level ports are not included)


     def m_mux_top8(x0, x1, x2, x3, x4, x5, x6, x7, y, sel):
         inputs = (x0,x1,x2,x3,x4,x5,x6,x7,)
         locallist = [Signal(xx.val) for xx in inputs]
         for xx,ll in zip(inputs,locallist):
             ll.assign(xx)
         print(ll)
         gmux = m_mux(locallist, y, sel)
         return gmux

And finally a short test and conversion:

     # ---[Simple Testbench and Conversion]---
     x = [Signal(intbv(init)[12:])
          for init in (15, 31, 63, 127, 255, 511, 1023, 2047,)]
     y = Signal(intbv(0)[12:])
     sel = Signal(intbv(0, min=0, max=len(x)))
     tbdut = m_mux_top(y, sel)
     def test(tbdut):
         @instance
         def tbstim():
             for ii in range(len(x)):
                 sel.next = ii
                 yield delay(4)
                 assert y == x[ii], " x[%d] %d, y %d" % \
                                    (ii,int(x[ii]),int(y))
         return tbstim, tbdut

     Simulation(test(m_mux_top(y,sel))).run()
     Simulation(test(m_mux_top8(*x, y=y, sel=sel))).run()
     toVerilog(m_mux_top, y=y, sel=sel)
     toVerilog(m_mux_top8, *x, y=y, sel=sel)

Regards,
Chris

----------------------------------------------------------------
The converted Verilog
----------------------------------------------------------------
%less m_mux_top.v
// File: m_mux_top.v
// Generated by MyHDL 0.9dev
// Date: Fri Feb 14 08:33:37 2014

`timescale 1ns/10ps

module m_mux_top8 (
     y,
     sel
);

output [11:0] y;
reg [11:0] y;
input [2:0] sel;

always @(sel) begin: M_MUX_TOP_GMUX_RTL
     case (sel)
         0: y = 15;
         1: y = 31;
         2: y = 63;
         3: y = 127;
         4: y = 255;
         5: y = 511;
         6: y = 1023;
         default: y = 2047;
     endcase
end

endmodule

In [109]: %less m_mux_top8.v
// File: m_mux_top8.v
// Generated by MyHDL 0.9dev
// Date: Fri Feb 14 08:33:37 2014

`timescale 1ns/10ps

module m_mux_top8 (
     x0,
     x1,
     x2,
     x3,
     x4,
     x5,
     x6,
     x7,
     y,
     sel
);

input [11:0] x0;
input [11:0] x1;
input [11:0] x2;
input [11:0] x3;
input [11:0] x4;
input [11:0] x5;
input [11:0] x6;
input [11:0] x7;
output [11:0] y;
wire [11:0] y;
input [2:0] sel;

wire [11:0] locallist [0:8-1];

assign y = locallist[sel];

endmodule


On 2/10/2014 7:29 PM, Carlos Silva wrote:
> Hi,
>
> I´ve had been using MyHDL to generate dynamic Verilog code directly from a
> python program. Leaving apart some natural difficulties due to my need of
> dynamic number of inputs and input widths, I´m facing a problem with an
> instance that I thought will be simple to implement, but returned me an
> unexpected error.
>
> Im trying to implement a simple 8x3 multiplexer and I receive the following
> error:
>
> Traceback (most recent call last):
>    File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
>      N_TRUNC, N_CALIB)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line
> 135, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line
> 168, in _analyzeGens
>      raise ConversionError(_error.UnsupportedType, n, info)
> myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182:
> Object type is not supported in this context: in4
>
> The related parts of my code are:
>
>      n0 = Signal(intbv(15))[12:0]
>      n1 = Signal(intbv(31))[12:0]
>      n2 = Signal(intbv(63))[12:0]
>      n3 = Signal(intbv(127))[12:0]
>      n4 = Signal(intbv(255))[12:0]
>      n5 = Signal(intbv(511))[12:0]
>      n6 = Signal(intbv(1023))[12:0]
>      n7 = Signal(intbv(2047))[12:0]
>      db6 = Signal(intbv(0)[12:0])
>      n = Signal(intbv(0)[3:0])
>      U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)
>
> # Multiplexer (8 inputs, 3 bits selector)
> def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
>      @always_comb
>      def logic():
>          if sel == 0x0:
>              out.next = in0
>          elif sel == 0x1:
>              out.next = in1
>          elif sel == 0x2:
>              out.next = in2
>          elif sel == 0x3:
>              out.next = in3
>          elif sel == 0x4:
>              out.next = in4
>          elif sel == 0x5:
>              out.next = in5
>          elif sel == 0x6:
>              out.next = in6
>          else:
>              out.next = in7
>      return instances()
>
>
> I have edited manually the code of "_extractHierarchy" with some print
> statements to obtain the types for each input, and it stops at in4, with the
> following sequence of prints:
>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._intbv.intbv'>
>
>
> The original type of all the inputs is <class 'myhdl._intbv.intbv'>.
>
> Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.
>
>
> Any sugestions?
>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] <at> always_comb - Conversion Error

[Carlos S. <car...@sa...>]

Thanks, Chris

I apreciate your help.

That solved my problem. :)

Re: [myhdl-list] @always_comb - Conversion Error

[Jan D. <ja...@ja...>]

Did you simulate this?

I don't think so. But you should:

http://www.myhdl.org/doc/current/manual/conversion.html#simulate-first

Any operation on a Signal, including slicing, operates on the
underlying value. In particular, slicing a Signal of an intbv
returns an intbv, not a Signal.

In other words, the "signal" aspect of your inputs is gone
and I don't see how this can work. And if it doesn't work,
conclusions about convertibility are meaningless.

On 02/11/2014 02:29 AM, Carlos Silva wrote:
> Hi,
>
> I´ve had been using MyHDL to generate dynamic Verilog code directly from a
> python program. Leaving apart some natural difficulties due to my need of
> dynamic number of inputs and input widths, I´m facing a problem with an
> instance that I thought will be simple to implement, but returned me an
> unexpected error.
>
> Im trying to implement a simple 8x3 multiplexer and I receive the following
> error:
>
> Traceback (most recent call last):
>    File "C:\ECLIPSE\Scales_verilog\DYN\average_hw.py", line 624, in <module>
>      N_TRUNC, N_CALIB)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_toVerilog.py", line
> 135, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "C:\Python27\lib\site-packages\myhdl\conversion\_analyze.py", line
> 168, in _analyzeGens
>      raise ConversionError(_error.UnsupportedType, n, info)
> myhdl.ConversionError: File C:\ECLIPSE\Scales_verilog\DYN\HDW.py, line 182:
> Object type is not supported in this context: in4
>
> The related parts of my code are:
>
>      n0 = Signal(intbv(15))[12:0]
>      n1 = Signal(intbv(31))[12:0]
>      n2 = Signal(intbv(63))[12:0]
>      n3 = Signal(intbv(127))[12:0]
>      n4 = Signal(intbv(255))[12:0]
>      n5 = Signal(intbv(511))[12:0]
>      n6 = Signal(intbv(1023))[12:0]
>      n7 = Signal(intbv(2047))[12:0]
>      db6 = Signal(intbv(0)[12:0])
>      n = Signal(intbv(0)[3:0])
>      U_25 = Mux_8(n0, n1, n2, n3, n4, n5, n6, n7, db6, n)
>
> # Multiplexer (8 inputs, 3 bits selector)
> def Mux_8(in0, in1, in2, in3, in4, in5, in6, in7, out, sel):
>      @always_comb
>      def logic():
>          if sel == 0x0:
>              out.next = in0
>          elif sel == 0x1:
>              out.next = in1
>          elif sel == 0x2:
>              out.next = in2
>          elif sel == 0x3:
>              out.next = in3
>          elif sel == 0x4:
>              out.next = in4
>          elif sel == 0x5:
>              out.next = in5
>          elif sel == 0x6:
>              out.next = in6
>          else:
>              out.next = in7
>      return instances()
>
>
> I have edited manually the code of "_extractHierarchy" with some print
> statements to obtain the types for each input, and it stops at in4, with the
> following sequence of prints:
>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._Signal._Signal'>
> <class 'myhdl._intbv.intbv'>
>
>
> The original type of all the inputs is <class 'myhdl._intbv.intbv'>.
>
> Using python 2.7 under Eclipse with Pydev and MyHDL 0.8.
>
>
> Any sugestions?
>
>
>
>
> ------------------------------------------------------------------------------
> Android apps run on BlackBerry 10
> Introducing the new BlackBerry 10.2.1 Runtime for Android apps.
> Now with support for Jelly Bean, Bluetooth, Mapview and more.
> Get your Android app in front of a whole new audience.  Start now.
> http://pubads.g.doubleclick.net/gampad/clk?id=124407151&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com