myhdl-list

[myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

What is it
==========
myhdl_tools is a eclectic collection of tools that have been
used in various projects and examples.  The tools assist in
simulation and FPGA build and other random tasks.

Main Features
=============

    * Clock, Reset, SignalQueue objects to simplify repetitive
      tasks in simulation.  Example, the Clock object simplifies
      clock generation in simulation and separately passing the
      clock frequency as a argument parameter to modules

    * FPGA build tools, automates the execution of the FPGA
      tools for specific development boards.  A MyHDL top-level
      module can be given to the tools and the ports will
      automatgically mapped to the board definition (if the
      port names match the pin names).

    * Board definitions, a collection of board definitions to
      be used with the FPGA build

    * Cosimulation tools


Where to get it
===============
The repository is hosted on bitbucket:
https://bitbucket.org/cfelton/myhdl_tools/

release download:
https://bitbucket.org/cfelton/myhdl_tools/downloads

and is available on PiPy.  The package can be installed
with pip etc.

    >> pip install myhdl_tools

License
=======
LGPL

Documentation
=============
The current documentation is available at the landing page [1]
on bitbucket.  The sphinx documents will be available in one
of the future releases :)

Background
==========
Roughly a year ago I "dumped" a bunch of common tools into a
package.  These tools did not fit with a particular project.
In some cases I wanted a test area for possible future myhdl
additions.  I first used some of the tools in this package in
the MyHDL LED example [2][3] to automate the FPGA toolflow.
I then used it in the examples for DesignWest 2013 [4][5]
(ESC, EELive) to reduce the number of lines of code in the
examples, and again with the PyOhio workshop [6][7], again to
automate the FPGA flow so the attendees could focus on the HDL
design and not the toolflow.  I have also used it in a couple
of projects [8][9].

Although this is a random collection of  tools these tools
significantly simplify an FPGA flow for MyHDL.

Discussion and Development
==========================
Discussions can occur on the MyHDL mailing-list (assuming
no one has an objection), contributions are welcomed
(encouraged), pull requests can be submitted to the bitbucket
repository [1].  Bugs and feature requests can also be logged
on the bitbucket repository.  An straight-forward contribution
is more board definitions.

Regards,
Chris Felton

[1] https://bitbucket.org/cfelton/myhdl_tools/overview
[2] http://www.fpgarelated.com/showarticle/25.php
[3] 
https://bitbucket.org/cfelton/examples/src/tip/stroby/compile_stroby.py?at=default
[4] 
http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329slides_felton_24apr2013.pdf
[5] http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329paper_felton.pdf
[6] http://www.fpgarelated.com/showarticle/433.php
[7] http://www.fpgarelated.com/showarticle/437.php
[8] https://bitbucket.org/cfelton/examples
[9] https://github.com/cfelton/minnesota
      note on [9] github was the first home but is a mirror of
      the actual development repo on bitbucket.  Only major
      updates are pushed over.  The mn pkg main IP core at this
      point is the fpgalink core [10], bitbukcet version [11]
[10] https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
[11] https://bitbucket.org/cfelton/minnesota

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 29.11.2013 18:40, schrieb Christopher Felton:
>
> What is it
> ==========
> myhdl_tools is a eclectic collection of tools that have been
> used in various projects and examples.  The tools assist in
> simulation and FPGA build and other random tasks.

Looks interesting, especially since it creates a command line workflow
for synthesis which I have never used so far.
However, here are a few issues I encountered while trying the example
from the overview webpage (Windows7, xilinx ise 14.1):

> C:\Users\thomas\devel\hdl>py -2.7-32 -O xula.py
> ('HDL PORTS:  ', {'chan': None})
> ('HDL PARAMS: ', {})
> ** ToVerilogWarning: Output port is read internally: chan
>    checking ./xilinx/xula.v
>    moving xula.v --> ./xilinx/
>    checking ./xilinx/tb_xula.v
>    moving tb_xula.v --> ./xilinx/
> Traceback (most recent call last):
>   File "xula.py", line 20, in <module>
>     brd.run()#"vhdl")
>   File "C:\Python27\lib\site-packages\myhdl_tools\_xilinx.py", line 283, in run
>     self.convert(to=use)
>   File "C:\Python27\lib\site-packages\myhdl_tools\_fpga.py", line 156, in convert
>     shutil.move(src,self._path)
>   File "C:\Python27\lib\shutil.py", line 299, in move
>     copy2(src, real_dst)
>   File "C:\Python27\lib\shutil.py", line 128, in copy2
>     copyfile(src, dst)
>   File "C:\Python27\lib\shutil.py", line 83, in copyfile
>     with open(dst, 'wb') as fdst:
> IOError: [Errno 22] invalid mode ('wb') or filename: './xilinx/'
>
> C:\Users\thomas\devel\hdl>

I have to delete the 'xilinx' file that was created, and create
a 'xilinx' directory before running the code, then it works.

Trying vhdl instead of verilog, by using 'brd.run("vhdl")' gives this:

> C:\Users\thomas\devel\hdl>py -2.7-32 -O xula.py
> ('HDL PORTS:  ', {'chan': None})
> ('HDL PARAMS: ', {})
> ** ToVHDLWarning: Output port is read internally: chan
>    checking ./xilinx/xula.vhd
>    moving xula.vhd --> ./xilinx/
>    checking ./xilinx/tb_xula.vhd
>    checking ./xilinx/pck_myhdl_08dev.vhd
> Traceback (most recent call last):
>   File "xula.py", line 20, in <module>
>     brd.run("vhdl")
>   File "C:\Python27\lib\site-packages\myhdl_tools\_xilinx.py", line 284, in run
>     self.create_ucf(filename=self.name+'.ucf')
> AttributeError: 'XilinxFPGA' object has no attribute 'name'
>
> C:\Users\thomas\devel\hdl>

Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 11/30/2013 10:24 AM, Thomas Heller wrote:
> Am 29.11.2013 18:40, schrieb Christopher Felton:
>>
>> What is it
>> ==========
>> myhdl_tools is a eclectic collection of tools that have been
>> used in various projects and examples.  The tools assist in
>> simulation and FPGA build and other random tasks.
>
> Looks interesting, especially since it creates a command line workflow
> for synthesis which I have never used so far.
> However, here are a few issues I encountered while trying the example
> from the overview webpage (Windows7, xilinx ise 14.1):
>

Yes, the Python controlled flow has been huge
for formal and infomral workshops.  People can
focus on the HDL and the results (working HW)
vs. trying to get the FPGA tools installed and
learning yet another IDE/tool.

<snip>
>
> I have to delete the 'xilinx' file that was created, and create
> a 'xilinx' directory before running the code, then it works.
>
> Trying vhdl instead of verilog, by using 'brd.run("vhdl")' gives this:
>
<snip>
>
> Thomas
>

Thanks for the feedback!  I have fixed these
issues and will push a new release, 0.0.2
ASAP.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 02.12.2013 16:48, schrieb Christopher Felton:
> Thanks for the feedback!  I have fixed these
> issues and will push a new release, 0.0.2
> ASAP.

Not so quick :-)

Here are two other issues I found:

1. The ucf file is not added to the project file, so the pin mappings
are not used.

2. I use a spartan3a in FT256 package, the pin names are strings.
The original code creates wrong pin names in the ucf file, attached
is a patch that I used.

Thanks,
Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/2/2013 12:38 PM, Thomas Heller wrote:
> Am 02.12.2013 16:48, schrieb Christopher Felton:
>> Thanks for the feedback!  I have fixed these
>> issues and will push a new release, 0.0.2
>> ASAP.
>
> Not so quick :-)
>
> Here are two other issues I found:

Thanks, I will look into these as well, good
thing I released this with only a patch version
designator (major.minor.patch).

>
> 1. The ucf file is not added to the project file, so the pin mappings
> are not used.

That is odd, I did not see this with the system
I tested on, obviously if the UCF is not add to
the project none of the pins or timing constraints
would be used, hmm.

>
> 2. I use a spartan3a in FT256 package, the pin names are strings.
> The original code creates wrong pin names in the ucf file, attached
> is a patch that I used.

I have used BGA packages with "string" pin definitions
and it has worked ok.  I must of broke something?

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/2/13 3:21 PM, Christopher Felton wrote:
> On 12/2/2013 12:38 PM, Thomas Heller wrote:
>> Am 02.12.2013 16:48, schrieb Christopher Felton:
>>> Thanks for the feedback!  I have fixed these
>>> issues and will push a new release, 0.0.2
>>> ASAP.
>>
>> Not so quick :-)
>>
>> Here are two other issues I found:
>>
>> 1. The ucf file is not added to the project file, so the pin mappings
>> are not used.
>>
>> 2. I use a spartan3a in FT256 package, the pin names are strings.
>> The original code creates wrong pin names in the ucf file, attached
>> is a patch that I used.

I uploaded version 0.0.2 to pypi and to
bitbucket [1].  Thanks again for the feedback.

Regards,
Chris

[1] https://bitbucket.org/cfelton/myhdl_tools/downloads

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 04:41, schrieb Christopher Felton:
>
> I uploaded version 0.0.2 to pypi and to
> bitbucket [1].  Thanks again for the feedback.
>
Thanks for the quick fixes.

Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/2/13 12:38 PM, Thomas Heller wrote:
> Am 02.12.2013 16:48, schrieb Christopher Felton:
>> Thanks for the feedback!  I have fixed these
>> issues and will push a new release, 0.0.2
>> ASAP.
>
> Not so quick :-)
>
> Here are two other issues I found:
>
> 1. The ucf file is not added to the project file, so the pin mappings
> are not used.
>

I don't observe the same behavior, if you look
at the <proj>.tcl file in the xilinx directory
you should see something like the following:

     cd ./xilinx/
     # set ucf file:
     set constraints_file xula.ucf

https://gist.github.com/cfelton/7763151

I am testing with ISE 14.5 on LUbuntu.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 03:51, schrieb Christopher Felton:
> On 12/2/13 12:38 PM, Thomas Heller wrote:
>> Am 02.12.2013 16:48, schrieb Christopher Felton:
>>> Thanks for the feedback!  I have fixed these
>>> issues and will push a new release, 0.0.2
>>> ASAP.
>>
>> Not so quick :-)
>>
>> Here are two other issues I found:
>>
>> 1. The ucf file is not added to the project file, so the pin mappings
>> are not used.
>>
>
> I don't observe the same behavior, if you look
> at the <proj>.tcl file in the xilinx directory
> you should see something like the following:
>
>       cd ./xilinx/
>       # set ucf file:
>       set constraints_file xula.ucf

True, but the pin mappings (or the timing constraints) from the ucf-file
are not used by the synthesis.  Looking into the .csv file that is
created, I don't see located pins.

Here is what I observe:

Using fpga.run() to run synthesis, the ucf file is not used.
Starting the ISE GUI, I add the ucf-file to the sources file list,
and running fpga.run() again, the ucf file is used, and the pins are 
located.  Starting fpga.run() again gies the same result.

Remove the xilinx subdirectory completely.
I add 'xfile add myfile.ucf' to the code that generates the tcl
script, start fpga.run(), then everything works.
Starting fpga.run() a second time, I get an error that 'myfile.ucf'
is already part of the projects and sysnthesis fails.
I have to remove the xilinx subdirectory completely, then fpga.run()
works again.

Whatever this means.

Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

<snip>
>
> Here is what I observe:
>
> Using fpga.run() to run synthesis, the ucf file is not used.
> Starting the ISE GUI, I add the ucf-file to the sources file list,
> and running fpga.run() again, the ucf file is used, and the pins are
> located.  Starting fpga.run() again gies the same result.
>
> Remove the xilinx subdirectory completely.
> I add 'xfile add myfile.ucf' to the code that generates the tcl
> script, start fpga.run(), then everything works.
> Starting fpga.run() a second time, I get an error that 'myfile.ucf'
> is already part of the projects and sysnthesis fails.
> I have to remove the xilinx subdirectory completely, then fpga.run()
> works again.
>
> Whatever this means.
>
> Thomas
>

Ugh, one of the reasons I hesitate and was uncertain
if I wanted to release this project or not,
compatibility and version issues can be difficult to
resolve :)

I have some confidence that it the UCF is applied, at
least on some version of ISE and some version of OS,
otherwise this would have never worked:
https://twitter.com/FeltonChris/status/360587567718080514

I will play around and see if there is a better
solution.  I do remember running into the the xfile
add issue.  Maybe similar to the Altera TCL scripts,
there is a way to force a *new* project every run - then
the xfile would work.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Thomas H. <th...@ct...>]

Am 03.12.2013 20:42, schrieb Christopher Felton:
> Ugh, one of the reasons I hesitate and was uncertain
> if I wanted to release this project or not,
> compatibility and version issues can be difficult to
> resolve :)

I also find it great that yo released it.

Software releases are done so that customers find the bugs,
or maybe even submit patches.

Thanks,
Thomas

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Kamyar M. <ka...@ie...>]

Hi Chris,
Do you happen to have any plans for adding support for the Altera flow to
your toolset? As FPGA flows usually have a lot it common, do you think it
would be possible to have a sort of modular back-end structure for each
vendor, providing specifics for a more general front-end? How easy would it
be to implement this sort of modularity in myhdl_tools?


On Fri, Nov 29, 2013 at 9:10 PM, Christopher Felton
<chr...@gm...>wrote:

>
> What is it
> ==========
> myhdl_tools is a eclectic collection of tools that have been
> used in various projects and examples.  The tools assist in
> simulation and FPGA build and other random tasks.
>
> Main Features
> =============
>
>     * Clock, Reset, SignalQueue objects to simplify repetitive
>       tasks in simulation.  Example, the Clock object simplifies
>       clock generation in simulation and separately passing the
>       clock frequency as a argument parameter to modules
>
>     * FPGA build tools, automates the execution of the FPGA
>       tools for specific development boards.  A MyHDL top-level
>       module can be given to the tools and the ports will
>       automatgically mapped to the board definition (if the
>       port names match the pin names).
>
>     * Board definitions, a collection of board definitions to
>       be used with the FPGA build
>
>     * Cosimulation tools
>
>
> Where to get it
> ===============
> The repository is hosted on bitbucket:
> https://bitbucket.org/cfelton/myhdl_tools/
>
> release download:
> https://bitbucket.org/cfelton/myhdl_tools/downloads
>
> and is available on PiPy.  The package can be installed
> with pip etc.
>
>     >> pip install myhdl_tools
>
> License
> =======
> LGPL
>
> Documentation
> =============
> The current documentation is available at the landing page [1]
> on bitbucket.  The sphinx documents will be available in one
> of the future releases :)
>
> Background
> ==========
> Roughly a year ago I "dumped" a bunch of common tools into a
> package.  These tools did not fit with a particular project.
> In some cases I wanted a test area for possible future myhdl
> additions.  I first used some of the tools in this package in
> the MyHDL LED example [2][3] to automate the FPGA toolflow.
> I then used it in the examples for DesignWest 2013 [4][5]
> (ESC, EELive) to reduce the number of lines of code in the
> examples, and again with the PyOhio workshop [6][7], again to
> automate the FPGA flow so the attendees could focus on the HDL
> design and not the toolflow.  I have also used it in a couple
> of projects [8][9].
>
> Although this is a random collection of  tools these tools
> significantly simplify an FPGA flow for MyHDL.
>
> Discussion and Development
> ==========================
> Discussions can occur on the MyHDL mailing-list (assuming
> no one has an objection), contributions are welcomed
> (encouraged), pull requests can be submitted to the bitbucket
> repository [1].  Bugs and feature requests can also be logged
> on the bitbucket repository.  An straight-forward contribution
> is more board definitions.
>
> Regards,
> Chris Felton
>
> [1] https://bitbucket.org/cfelton/myhdl_tools/overview
> [2] http://www.fpgarelated.com/showarticle/25.php
> [3]
>
> https://bitbucket.org/cfelton/examples/src/tip/stroby/compile_stroby.py?at=default
> [4]
>
> http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329slides_felton_24apr2013.pdf
> [5]
> http://myhdl.org/lib/exe/fetch.php/users:cfelton:esc-329paper_felton.pdf
> [6] http://www.fpgarelated.com/showarticle/433.php
> [7] http://www.fpgarelated.com/showarticle/437.php
> [8] https://bitbucket.org/cfelton/examples
> [9] https://github.com/cfelton/minnesota
>       note on [9] github was the first home but is a mirror of
>       the actual development repo on bitbucket.  Only major
>       updates are pushed over.  The mn pkg main IP core at this
>       point is the fpgalink core [10], bitbukcet version [11]
> [10] https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
> [11] https://bitbucket.org/cfelton/minnesota
>
>
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics
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> _______________________________________________
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/2/2013 3:12 PM, Kamyar Mohajerani wrote:
> Hi Chris,
> Do you happen to have any plans for adding support for the Altera flow to
> your toolset? As FPGA flows usually have a lot it common, do you think it
> would be possible to have a sort of modular back-end structure for each
> vendor, providing specifics for a more general front-end? How easy would it
> be to implement this sort of modularity in myhdl_tools?
>

Yes, I have all the pieces to add the Altera
flow.  Unfortunately, when I setup my machine
I only tested the Xilinx ISE install (I needed
ISE at the time).  When I went to install
Quartus ... no luck with the distro I used.

I have to take some time and find the best distro
to install both toolflows.  I am told, if I want
to be safe I have to use CentOS.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Kamyar M. <ka...@ie...>]

I here have ISE 14.7 and Quartus 13.1 installed and working on Fedora 19.
CentOS is very stable and a safe bet but at the same time some of the
rather old packages make it somehow uncomfortable to be used as
the development environment.
Let us know when you have any of the quartus stuff ready for
release/testing.
And let me know if there's anything I can help with.

Regards,
Kamyar


On Tue, Dec 3, 2013 at 12:51 AM, Christopher Felton
<chr...@gm...>wrote:

> On 12/2/2013 3:12 PM, Kamyar Mohajerani wrote:
> > Hi Chris,
> > Do you happen to have any plans for adding support for the Altera flow to
> > your toolset? As FPGA flows usually have a lot it common, do you think it
> > would be possible to have a sort of modular back-end structure for each
> > vendor, providing specifics for a more general front-end? How easy would
> it
> > be to implement this sort of modularity in myhdl_tools?
> >
>
> Yes, I have all the pieces to add the Altera
> flow.  Unfortunately, when I setup my machine
> I only tested the Xilinx ISE install (I needed
> ISE at the time).  When I went to install
> Quartus ... no luck with the distro I used.
>
> I have to take some time and find the best distro
> to install both toolflows.  I am told, if I want
> to be safe I have to use CentOS.
>
> Regards,
> Chris
>
>
>
>
>
>
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics
> Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349351&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Alexander H. <ale...@gm...>]

Hi Chris

well, at least I am glad you released it! :-)
I also added some small improvements which made life easier for me
with these tools and hope you like them (bitbucket pull request).

Regarding the .ucf file: I can absolutely confirm the behaviour Thomas
described. If I add the .ucf file myself using
> brd.hdl_file_list.append('pone.ucf')
it works the first time and fails afterwards (Ubuntu 13.10 64bit, ISE 14.5).

Maybe a possible solution would be to find out in which config file
Xilinx stores the used project source files and modify this directly?
Alternatively, just deleting and recreating the xilinx directory every
time one does a run() should work, too!

Best,
Alex

2013/12/3 Christopher Felton <chr...@gm...>:
> <snip>
>>
>> Here is what I observe:
>>
>> Using fpga.run() to run synthesis, the ucf file is not used.
>> Starting the ISE GUI, I add the ucf-file to the sources file list,
>> and running fpga.run() again, the ucf file is used, and the pins are
>> located.  Starting fpga.run() again gies the same result.
>>
>> Remove the xilinx subdirectory completely.
>> I add 'xfile add myfile.ucf' to the code that generates the tcl
>> script, start fpga.run(), then everything works.
>> Starting fpga.run() a second time, I get an error that 'myfile.ucf'
>> is already part of the projects and sysnthesis fails.
>> I have to remove the xilinx subdirectory completely, then fpga.run()
>> works again.
>>
>> Whatever this means.
>>
>> Thomas
>>
>
> Ugh, one of the reasons I hesitate and was uncertain
> if I wanted to release this project or not,
> compatibility and version issues can be difficult to
> resolve :)
>
> I have some confidence that it the UCF is applied, at
> least on some version of ISE and some version of OS,
> otherwise this would have never worked:
> https://twitter.com/FeltonChris/status/360587567718080514
>
> I will play around and see if there is a better
> solution.  I do remember running into the the xfile
> add issue.  Maybe similar to the Altera TCL scripts,
> there is a way to force a *new* project every run - then
> the xfile would work.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Rapidly troubleshoot problems before they affect your business. Most IT
> organizations don't have a clear picture of how application performance
> affects their revenue. With AppDynamics, you get 100% visibility into your
> Java,.NET, & PHP application. Start your 15-day FREE TRIAL of AppDynamics Pro!
> http://pubads.g.doubleclick.net/gampad/clk?id=84349351&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

On 12/3/2013 2:10 PM, Alexander Hungenberg wrote:
> Hi Chris
>
> well, at least I am glad you released it! :-)
> I also added some small improvements which made life easier for me
> with these tools and hope you like them (bitbucket pull request).
>
> Regarding the .ucf file: I can absolutely confirm the behaviour Thomas
> described. If I add the .ucf file myself using
>> brd.hdl_file_list.append('pone.ucf')
> it works the first time and fails afterwards (Ubuntu 13.10 64bit, ISE 14.5).
>
> Maybe a possible solution would be to find out in which config file
> Xilinx stores the used project source files and modify this directly?
> Alternatively, just deleting and recreating the xilinx directory every
> time one does a run() should work, too!
>
> Best,
> Alex
>

Alex,

Thanks for the pull request!  The changes
are great!  I merged them yesterday.

I pushed a change to simply delete the project
file on each invocation, hopefully that is a
suitable workaround.

Regards,
Chris

Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

Thomas,

I pushed a couple changes last night to the
repo.  Think I fixed (finally?) the VHDL build
and added a work around for the UCF file.  I
simply delete the project file every time and
create a new one.  I did limited testing, I hope
to test more tonight and any luck will release
0.0.3.

Thanks again for all the feedback, this has been
fun collaborating!
Chris


On Tue, Dec 3, 2013 at 2:18 PM, Thomas Heller <th...@ct...> wrote:

> Am 03.12.2013 20:42, schrieb Christopher Felton:
> > Ugh, one of the reasons I hesitate and was uncertain
> > if I wanted to release this project or not,
> > compatibility and version issues can be difficult to
> > resolve :)
>
> I also find it great that yo released it.
>
> Software releases are done so that customers find the bugs,
> or maybe even submit patches.
>
> Thanks,
> Thomas
>
>
>
>
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Re: [myhdl-list] [ANN] myhdl_tools 0.0.1

[Christopher F. <chr...@gm...>]

>
> I pushed a couple changes last night to the
> repo.  Think I fixed (finally?) the VHDL build
> and added a work around for the UCF file.  I
> simply delete the project file every time and
> create a new one.  I did limited testing, I hope
> to test more tonight and any luck will release
> 0.0.3.
>

Little later than anticipated but I pushed out
0.0.3 [1][2].

Note on revisioning - I am using the major.minor.patch
revision scheme but considering 0.0 alpha and all
updates as patches till 0.1 :)

Regards,
Chris

[1] https://bitbucket.org/cfelton/myhdl_tools/downloads
[2] pip install myhdl_tools