Thread: [myhdl-list] attribute enum_encoding: string;
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From: David H. <da...@ad...> - 2013-09-03 21:25:27
|
Hello, When using ghdl for syntax checks, I get the following error for any
state machine where encoding="one_hot":
pcie_drx.vhd:137:11: no declaration for "enum_encoding"
I can resolve ghdl's complaints by adding
attribute enum_encoding: string;
to the generated .vhd file.
Is there a way to have this line included automatically in .vhd output? I
could add it via a shell script, but I'm wondering if there is "better way"
to do it. (or is GHDL in error?)
For example, here is an trimmed-down excerpt from the top of the .vhd file
showing where I add the line:
package pck_pcie_drx is
> attribute enum_encoding: string; <--- I need to add this line.
type t_enum_t_state_22 is (
>
IDLE,
THINK,
SEND_CMD,
ADVANCE
);
attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100 1000";
type t_enum_t_state_23 is (
> CMD,
> MWR_H0H1,
> MWR32_H2D0,
> MWR32_D1D2,
> MWR32_D3XX,
> MWR64_H2H3,
> MWR64_D0D1,
> DROP
> );
> attribute enum_encoding of t_enum_t_state_23: type is "00000001 00000010
> 00000100 00001000 00010000 00100000 01000000 10000000";
> end package pck_pcie_drx;
> library IEEE;
> etc...
- David
ps: Thank you for the fantastic MyHDL.
|
|
From: Christopher F. <chr...@gm...> - 2013-09-05 02:57:17
|
The following works without issue:
from myhdl import *
def m_think(clock,reset,thinking,sending,sent):
states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
state = Signal(states.IDLE)
@always_seq(clock.posedge, reset=reset)
def rtl():
thinking.next = False
sending.next = False
if state == states.IDLE:
state.next = states.THINK
elif state == states.THINK:
thinking.next = True
state.next = states.SEND_CMD
elif state == states.SEND_CMD:
sending.next = True
state.next = states.ADVANCE
elif state == states.ADVANCE:
sent.next = sent+1
state.next = states.IDLE
else:
assert False, "Invalid states %s"%(state)
return rtl
def convert():
clock = Signal(bool(0))
reset = ResetSignal(0,active=0,async=True)
thinking = Signal(bool(0))
sending = Signal(bool(0))
sent = Signal(intbv(0,min=0,max=10e12))
toVHDL(m_think,clock,reset,thinking,sending,sent)
if __name__ == '__main__':
convert()
>> ghdl -a pck_myhdl_09.vhd m_think.vhd
>> ghdl -e m_think
https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default
Note, I didn't test that the above example worked
functionally. I just put it together to demonstrate
the "enum" type in VHDL is working. In addition I am
using a development snapshot but there hasn't been any
changes in this area in the development, it is identical
to the 0.8.
Regards,
Chris
On 9/3/13 2:48 PM, David Holl wrote:
> Hello, When using ghdl for syntax checks, I get the following error for
> any state machine where encoding="one_hot":
> pcie_drx.vhd:137:11: no declaration for "enum_encoding"
>
> I can resolve ghdl's complaints by adding
> Â attribute enum_encoding: string;
> to the generated .vhd file.
>
> Is there a way to have this line included automatically in .vhd output?
> Â I could add it via a shell script, but I'm wondering if there is
> "better way" to do it. Â (or is GHDL in error?)
>
>
> For example, here is an trimmed-down excerpt from the top of the .vhd
> file showing where I add the line:
>
> package pck_pcie_drx is
> Â Â attribute enum_encoding: string; Â <--- I need to add this line.
>
> Â Â type t_enum_t_state_22 is (
>
> Â Â IDLE,
>
> Â Â THINK,
>
> Â Â SEND_CMD,
>
> Â Â ADVANCE
>
> );
>
> attribute enum_encoding of t_enum_t_state_22: type is "0001 0010
> 0100 1000";
>
> Â Â type t_enum_t_state_23 is (
> Â Â CMD,
> Â Â MWR_H0H1,
> Â Â MWR32_H2D0,
> Â Â MWR32_D1D2,
> Â Â MWR32_D3XX,
> Â Â MWR64_H2H3,
> Â Â MWR64_D0D1,
> Â Â DROP
> );
> attribute enum_encoding of t_enum_t_state_23: type is "00000001
> 00000010 00000100 00001000 00010000 00100000 01000000 10000000";
> end package pck_pcie_drx;
> library IEEE;
> etc...
>
>
>
>
> - David
> Â ps: Â Thank you for the fantastic MyHDL.
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
|
|
From: Angel E. <ang...@gm...> - 2013-09-05 04:49:26
|
Chris,
I have not followed this in much detail so please excuse me if this is
obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
a builtin enum class. I think we should make sure that we make it
possible to use it if MyHDL is ever ported to Python 3.
Cheers,
Angel
On Thu, Sep 5, 2013 at 4:57 AM, Christopher Felton
<chr...@gm...> wrote:
> The following works without issue:
>
> from myhdl import *
>
> def m_think(clock,reset,thinking,sending,sent):
>
> states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
> state = Signal(states.IDLE)
>
> @always_seq(clock.posedge, reset=reset)
> def rtl():
> thinking.next = False
> sending.next = False
> if state == states.IDLE:
> state.next = states.THINK
> elif state == states.THINK:
> thinking.next = True
> state.next = states.SEND_CMD
> elif state == states.SEND_CMD:
> sending.next = True
> state.next = states.ADVANCE
> elif state == states.ADVANCE:
> sent.next = sent+1
> state.next = states.IDLE
> else:
> assert False, "Invalid states %s"%(state)
>
> return rtl
>
> def convert():
> clock = Signal(bool(0))
> reset = ResetSignal(0,active=0,async=True)
> thinking = Signal(bool(0))
> sending = Signal(bool(0))
> sent = Signal(intbv(0,min=0,max=10e12))
>
> toVHDL(m_think,clock,reset,thinking,sending,sent)
>
> if __name__ == '__main__':
> convert()
>
> >> ghdl -a pck_myhdl_09.vhd m_think.vhd
> >> ghdl -e m_think
>
> https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default
>
> Note, I didn't test that the above example worked
> functionally. I just put it together to demonstrate
> the "enum" type in VHDL is working. In addition I am
> using a development snapshot but there hasn't been any
> changes in this area in the development, it is identical
> to the 0.8.
>
> Regards,
> Chris
>
> On 9/3/13 2:48 PM, David Holl wrote:
>> Hello, When using ghdl for syntax checks, I get the following error for
>> any state machine where encoding="one_hot":
>> pcie_drx.vhd:137:11: no declaration for "enum_encoding"
>>
>> I can resolve ghdl's complaints by adding
>> Â attribute enum_encoding: string;
>> to the generated .vhd file.
>>
>> Is there a way to have this line included automatically in .vhd output?
>> Â I could add it via a shell script, but I'm wondering if there is
>> "better way" to do it. Â (or is GHDL in error?)
>>
>>
>> For example, here is an trimmed-down excerpt from the top of the .vhd
>> file showing where I add the line:
>>
>> package pck_pcie_drx is
>> Â Â attribute enum_encoding: string; Â <--- I need to add this line.
>>
>> Â Â type t_enum_t_state_22 is (
>>
>> Â Â IDLE,
>>
>> Â Â THINK,
>>
>> Â Â SEND_CMD,
>>
>> Â Â ADVANCE
>>
>> );
>>
>> attribute enum_encoding of t_enum_t_state_22: type is "0001 0010
>> 0100 1000";
>>
>> Â Â type t_enum_t_state_23 is (
>> Â Â CMD,
>> Â Â MWR_H0H1,
>> Â Â MWR32_H2D0,
>> Â Â MWR32_D1D2,
>> Â Â MWR32_D3XX,
>> Â Â MWR64_H2H3,
>> Â Â MWR64_D0D1,
>> Â Â DROP
>> );
>> attribute enum_encoding of t_enum_t_state_23: type is "00000001
>> 00000010 00000100 00001000 00010000 00100000 01000000 10000000";
>> end package pck_pcie_drx;
>> library IEEE;
>> etc...
>>
>>
>>
>>
>> - David
>> Â ps: Â Thank you for the fantastic MyHDL.
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
>> Discover the easy way to master current and previous Microsoft technologies
>> and advance your career. Get an incredible 1,500+ hours of step-by-step
>> tutorial videos with LearnDevNow. Subscribe today and save!
>> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
|
|
From: Christopher F. <chr...@gm...> - 2013-09-05 11:03:36
|
On 9/4/13 11:26 PM, David Holl wrote:
> Thank you for looking into it Chris. Â I confirm that the example code
> you sent works correctly with ghdl.
>
> But it still triggers the "no declaration" error in ghdl when I
> specify encoding='one_hot' for states:
>
> tensor(pts/0):~/m_think> diff old/m_think.py new/m_think.py
> 5c5
> < Â Â states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
> ---
> > Â Â states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE',
> encoding='one_hot')
>
Sorry for the confusion, yes I forgot to add the "encoding='one_hot'".
I have updated the example, for me I don't get the error, here
is a snip of the converted code
type t_enum_states_1 is (
IDLE,
THINK,
SEND_CMD,
ADVANCE
);
attribute enum_encoding of t_enum_states_1: type is "0001 0010 0100
1000";
>> ghdl -a pck_myhdl_09.vhd m_think.vhd
>> ghdl -e m_think
>> ghdl -r m_think
The version of GHDL I am using:
ghdl -v
GHDL 0.29 (20100109) [Sokcho edition]
Compiled with GNAT Version: 4.4.0 20080314 (experimental)
mcode code generator
Written by Tristan Gingold
I update the exampe:
https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py
Regards,
Chris
>
> tensor(pts/0):~/m_think> python m_think.pyÂ
> ** ToVHDLWarning: Output port is read internally: sent
> tensor(pts/0):~/m_think> ghdl -a pck_myhdl_08.vhd m_think.vhd   Â
> Â Â Â Â Â Â Â Â Â
> m_think.vhd:15:11: no declaration for "enum_encoding"
> /usr/lib/ghdl/bin/ghdl: compilation error
> tensor(pts/0):~/m_think> echo $?
> 1
>
> I've attached the modify python code and generated vhdl.
>
> Thank you,
> David
>
>
> On Wed, Sep 4, 2013 at 10:57 PM, Christopher Felton
> <chr...@gm... <mailto:chr...@gm...>> wrote:
>
> The following works without issue:
>
> Â Â Â from myhdl import *
>
> Â Â Â def m_think(clock,reset,thinking,sending,sent):
>
> Â Â Â Â Â states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
> Â Â Â Â Â state = Signal(states.IDLE)
>
> Â Â Â Â Â @always_seq(clock.posedge, reset=reset)
> Â Â Â Â Â def rtl():
> Â Â Â Â Â Â Â thinking.next = False
> Â Â Â Â Â Â Â sending.next = False
> Â Â Â Â Â Â Â if state == states.IDLE:
> Â Â Â Â Â Â Â Â Â state.next = states.THINK
> Â Â Â Â Â Â Â elif state == states.THINK:
> Â Â Â Â Â Â Â Â Â thinking.next = True
> Â Â Â Â Â Â Â Â Â state.next = states.SEND_CMD
> Â Â Â Â Â Â Â elif state == states.SEND_CMD:
> Â Â Â Â Â Â Â Â Â sending.next = True
> Â Â Â Â Â Â Â Â Â state.next = states.ADVANCE
> Â Â Â Â Â Â Â elif state == states.ADVANCE:
> Â Â Â Â Â Â Â Â Â sent.next = sent+1
> Â Â Â Â Â Â Â Â Â state.next = states.IDLE
> Â Â Â Â Â Â Â else:
> Â Â Â Â Â Â Â Â Â assert False, "Invalid states %s"%(state)
>
> Â Â Â Â Â return rtl
>
> Â Â Â def convert():
> Â Â Â Â Â clock = Signal(bool(0))
> Â Â Â Â Â reset = ResetSignal(0,active=0,async=True)
> Â Â Â Â Â thinking = Signal(bool(0))
> Â Â Â Â Â sending = Signal(bool(0))
> Â Â Â Â Â sent = Signal(intbv(0,min=0,max=10e12))
>
> Â Â Â Â Â toVHDL(m_think,clock,reset,thinking,sending,sent)
>
> Â Â Â if __name__ == '__main__':
> Â Â Â Â Â convert()
>
> Â Â >> ghdl -a pck_myhdl_09.vhd m_think.vhd
> Â Â >> ghdl -e m_think
>
> https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default
>
> Note, I didn't test that the above example worked
> functionally. Â I just put it together to demonstrate
> the "enum" type in VHDL is working. Â In addition I am
> using a development snapshot but there hasn't been any
> changes in this area in the development, it is identical
> to the 0.8.
>
> Regards,
> Chris
>
> On 9/3/13 2:48 PM, David Holl wrote:
> > Hello, When using ghdl for syntax checks, I get the following
> error for
> > any state machine where encoding="one_hot":
> > pcie_drx.vhd:137:11: no declaration for "enum_encoding"
> >
> > I can resolve ghdl's complaints by adding
> > Â  attribute enum_encoding: string;
> > to the generated .vhd file.
> >
> > Is there a way to have this line included automatically in .vhd
> output?
> > Â I could add it via a shell script, but I'm wondering if there is
> > "better way" to do it. Â (or is GHDL in error?)
> >
> >
> > For example, here is an trimmed-down excerpt from the top of the .vhd
> > file showing where I add the line:
> >
> > Â Â package pck_pcie_drx is
> >   Â  Â  attribute enum_encoding: string; Â <--- I need
> to add this line.
> >
> >   Â  Â  type t_enum_t_state_22 is (
> >
> >   Â  Â  IDLE,
> >
> >   Â  Â  THINK,
> >
> >   Â  Â  SEND_CMD,
> >
> >   Â  Â  ADVANCE
> >
> > Â Â );
> >
> > Â Â attribute enum_encoding of t_enum_t_state_22: type is "0001
> 0010
> > Â Â 0100 1000";
> >
> >   Â  Â  type t_enum_t_state_23 is (
> >   Â  Â  CMD,
> >   Â  Â  MWR_H0H1,
> >   Â  Â  MWR32_H2D0,
> >   Â  Â  MWR32_D1D2,
> >   Â  Â  MWR32_D3XX,
> >   Â  Â  MWR64_H2H3,
> >   Â  Â  MWR64_D0D1,
> >   Â  Â  DROP
> > Â Â );
> > Â Â attribute enum_encoding of t_enum_t_state_23: type is "00000001
> > Â Â 00000010 00000100 00001000 00010000 00100000 01000000
> 10000000";
> > Â Â end package pck_pcie_drx;
> > Â Â library IEEE;
> > Â Â etc...
> >
> >
> >
> >
> > - David
> > Â  ps: Â Thank you for the fantastic MyHDL.
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012,
> more!
> > Discover the easy way to master current and previous Microsoft
> technologies
> > and advance your career. Get an incredible 1,500+ hours of
> step-by-step
> > tutorial videos with LearnDevNow. Subscribe today and save!
> >
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
> >
> >
> >
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> <mailto:myh...@li...>
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft
> technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> <mailto:myh...@li...>
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
|
|
From: Christopher F. <chr...@gm...> - 2013-09-05 11:10:14
|
On 9/4/13 11:49 PM, Angel Ezquerra wrote: > Chris, > > I have not followed this in much detail so please excuse me if this is > obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get > a builtin enum class. I think we should make sure that we make it > possible to use it if MyHDL is ever ported to Python 3. > > Cheers, > > Angel > > Yes, the "enum" is from the MyHDL package. Something might need to be done to be compatible with the latest version of Python 3 when we get there :) Regards, Chris |
|
From: Angel E. <ang...@gm...> - 2013-09-05 11:20:10
|
My point was that perhaps calling MyHDL enums "enum" which is a builtin type in Python 3.4 (I believe!) may cause trouble long term, since it may require having to modify existing MyHDL files. Cheers, Angel On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton <chr...@gm...> wrote: > On 9/4/13 11:49 PM, Angel Ezquerra wrote: >> Chris, >> >> I have not followed this in much detail so please excuse me if this is >> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get >> a builtin enum class. I think we should make sure that we make it >> possible to use it if MyHDL is ever ported to Python 3. >> >> Cheers, >> >> Angel >> >> > > Yes, the "enum" is from the MyHDL package. Something might > need to be done to be compatible with the latest version of > Python 3 when we get there :) > > Regards, > Chris > > > > ------------------------------------------------------------------------------ > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > Discover the easy way to master current and previous Microsoft technologies > and advance your career. Get an incredible 1,500+ hours of step-by-step > tutorial videos with LearnDevNow. Subscribe today and save! > http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
|
From: Christopher F. <chr...@gm...> - 2013-09-05 12:09:11
|
On 9/5/2013 6:20 AM, Angel Ezquerra wrote: > My point was that perhaps calling MyHDL enums "enum" which is a > builtin type in Python 3.4 (I believe!) may cause trouble long term, > since it may require having to modify existing MyHDL files. > > Cheers, > > Angel > I am sure there are other projects that will have to deal with the /enum/ collision(?). I don't think we would want to discourage the use of the myhdl.enum. It shouldn't be an issue with existing or developing code, it is assumed they are not using the py3.enum, the myhdl.enum will be in the namespace. The only issue would be if someone wanted to update old code with py3.enum in the future, I think is highly unlikely. Regards, Chris > On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton > <chr...@gm...> wrote: >> On 9/4/13 11:49 PM, Angel Ezquerra wrote: >>> Chris, >>> >>> I have not followed this in much detail so please excuse me if this is >>> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get >>> a builtin enum class. I think we should make sure that we make it >>> possible to use it if MyHDL is ever ported to Python 3. >>> >>> Cheers, >>> >>> Angel >>> >>> >> >> Yes, the "enum" is from the MyHDL package. Something might >> need to be done to be compatible with the latest version of >> Python 3 when we get there :) >> >> Regards, >> Chris >> >> |
|
From: Jan D. <ja...@ja...> - 2013-09-10 10:30:59
|
There are other similar case in the mean time due to Python additions, such as 'bin'. I propose to review all this when going to Python3, seems a good time make larger changes iff required. On 09/05/2013 01:20 PM, Angel Ezquerra wrote: > My point was that perhaps calling MyHDL enums "enum" which is a > builtin type in Python 3.4 (I believe!) may cause trouble long term, > since it may require having to modify existing MyHDL files. > > Cheers, > > Angel > > On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton > <chr...@gm...> wrote: >> On 9/4/13 11:49 PM, Angel Ezquerra wrote: >>> Chris, >>> >>> I have not followed this in much detail so please excuse me if this is >>> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get >>> a builtin enum class. I think we should make sure that we make it >>> possible to use it if MyHDL is ever ported to Python 3. >>> >>> Cheers, >>> >>> Angel >>> >>> >> >> Yes, the "enum" is from the MyHDL package. Something might >> need to be done to be compatible with the latest version of >> Python 3 when we get there :) >> >> Regards, >> Chris >> >> >> >> ------------------------------------------------------------------------------ >> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! >> Discover the easy way to master current and previous Microsoft technologies >> and advance your career. Get an incredible 1,500+ hours of step-by-step >> tutorial videos with LearnDevNow. Subscribe today and save! >> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list > > ------------------------------------------------------------------------------ > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > Discover the easy way to master current and previous Microsoft technologies > and advance your career. Get an incredible 1,500+ hours of step-by-step > tutorial videos with LearnDevNow. Subscribe today and save! > http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
|
From: David H. <da...@ad...> - 2013-09-05 13:20:58
Attachments:
signature.asc
|
On Thu, Sep 05, 2013 at 06:03:33AM -0500, Christopher Felton wrote:
> On 9/4/13 11:26 PM, David Holl wrote:
> > But it still triggers the "no declaration" error in ghdl when I specify encoding='one_hot' for states:
> > ...
> I have updated the example, for me I don't get the error, here is a snip of the converted code
>
> type t_enum_states_1 is (
> IDLE,
> THINK,
> SEND_CMD,
> ADVANCE
> );
> attribute enum_encoding of t_enum_states_1: type is "0001 0010 0100 1000";
hrm --- Yep, that's the code that I'm also generating.
> >> ghdl -a pck_myhdl_09.vhd m_think.vhd
> >> ghdl -e m_think
> >> ghdl -r m_think
But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;"
tensor(pts/0):~/m_think> diff -u m_think.vhd.orig m_think.vhd
--- m_think.vhd.orig 2013-09-05 08:31:50.002627130 -0400
+++ m_think.vhd 2013-09-05 08:37:51.481874280 -0400
@@ -6,6 +6,7 @@
package pck_m_think is
+attribute enum_encoding: string;
type t_enum_states_1 is (
IDLE,
THINK,
> The version of GHDL I am using:
> ghdl -v
> GHDL 0.29 (20100109) [Sokcho edition]
> Compiled with GNAT Version: 4.4.0 20080314 (experimental)
> mcode code generator
> Written by Tristan Gingold
I'm using ghdl from Debian's package repository ("jessie" aka "testing"). It looks like a similar version to yours with differences in the GNAT version and code generator.
tensor(pts/0):~/m_think> ghdl -v
GHDL 0.29 (20100109) [Sokcho edition]
Compiled with GNAT Version: 4.4.4
GCC back-end code generator
Written by Tristan Gingold.
|
|
From: Christopher F. <chr...@gm...> - 2013-09-05 13:29:01
|
<snip>
>
> But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;"
>
> tensor(pts/0):~/m_think> diff -u m_think.vhd.orig m_think.vhd
> --- m_think.vhd.orig 2013-09-05 08:31:50.002627130 -0400
> +++ m_think.vhd 2013-09-05 08:37:51.481874280 -0400
> @@ -6,6 +6,7 @@
>
> package pck_m_think is
>
> +attribute enum_encoding: string;
> type t_enum_states_1 is (
> IDLE,
> THINK,
>
I don't recall all the VHDL rules here off the top
of my head. I can test with some synthesis tools
as well and do some research. It is a small change
that can probably be added, but I have to do some
inquiring before I create a pull-request.
Best I can tell adding
attribute enum_encoding: string
should be harmless, just an additional attribute
http://quartushelp.altera.com/11.1/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm
Regards,
Chris
|
|
From: David H. <da...@ad...> - 2013-09-05 18:58:59
Attachments:
signature.asc
|
> <snip> > > But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;" > > I don't recall all the VHDL rules here off the top > of my head. I can test with some synthesis tools > as well and do some research. It is a small change > that can probably be added, but I have to do some > inquiring before I create a pull-request. If I could help with testing, I'd love to try any patch to apply this small change in my branch. (I had been using 0.8dev from hg before the 0.8 release, to get access to the fabulous modbv...) I'm just not sure where the best place is to add the attribute, since it only needs to be added once and not for every state machine. > Best I can tell adding > > attribute enum_encoding: string > > should be harmless, just an additional attribute > http://quartushelp.altera.com/11.1/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm > > Regards, > Chris My motive for adding the attribute is that I found ghdl will not complain of other potential syntax errors until after I resolve this one. In addition to behavioral test bench code, I apply syntax checks from ghdl, cver, iverilog, and verilator, because Xilinx's compiler is so painfully slow... :) I've found that if my model passes all those compilers, my behavioral tests, and Xilinx timing analysis, then my PCI Express DMA engine has a great chance of working correctly on the first try when I load it on a dev kit in Linux. :) |
|
From: Jan D. <ja...@ja...> - 2013-09-09 10:39:28
|
Mm, the attribute is declared in pck_myhdl but probably this is namespace issue. Iff a port uses an enum, then a top-level package is needed and the declaration is not seen, unlike when the enum type is declared in the architecture. Jan On 09/03/2013 09:48 PM, David Holl wrote: > Hello, When using ghdl for syntax checks, I get the following error > for any state machine where encoding="one_hot": pcie_drx.vhd:137:11: > no declaration for "enum_encoding" > > I can resolve ghdl's complaints by adding attribute enum_encoding: > string; to the generated .vhd file. > > Is there a way to have this line included automatically in .vhd > output? I could add it via a shell script, but I'm wondering if > there is "better way" to do it. (or is GHDL in error?) > > > For example, here is an trimmed-down excerpt from the top of the .vhd > file showing where I add the line: > > package pck_pcie_drx is attribute enum_encoding: string; <--- I need > to add this line. > > type t_enum_t_state_22 is ( > > IDLE, > > THINK, > > SEND_CMD, > > ADVANCE > > ); > > attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100 > 1000"; > > type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2, > MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding > of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000 > 00010000 00100000 01000000 10000000"; end package pck_pcie_drx; > library IEEE; etc... > > > > > - David ps: Thank you for the fantastic MyHDL. > > > > ------------------------------------------------------------------------------ > > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > Discover the easy way to master current and previous Microsoft > technologies and advance your career. Get an incredible 1,500+ hours > of step-by-step tutorial videos with LearnDevNow. Subscribe today and > save! > http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk > > > > > _______________________________________________ myhdl-list mailing > list myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
|
From: David H. <da...@ad...> - 2013-09-09 12:49:24
|
ugh! My asinine filesystem lockdowns had prevented any recent updates to
myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012. Updating to
the latest 0.8 fixed the problem.
The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package
declared before any other statements such as "use work.pck_myhdl_08.all;"
package pck_pcie_drx is
type t_enum_t_state_1 is (
SM_RESET,
...
(but my design does not use any enum's in the ports)
However in the vhdl from the latest 0.8, there is no top-level package, and
the code opens with
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity pcie_drx is
port (
user_clk: in std_logic;
...
Thank you Chris and Jan for looking into this!
- David
On Mon, Sep 9, 2013 at 6:25 AM, Jan Decaluwe <ja...@ja...> wrote:
> Mm, the attribute is declared in pck_myhdl but probably this
> is namespace issue. Iff a port uses an enum, then a top-level
> package is needed and the declaration is not seen, unlike
> when the enum type is declared in the architecture.
>
> Jan
>
> On 09/03/2013 09:48 PM, David Holl wrote:
> > Hello, When using ghdl for syntax checks, I get the following error
> > for any state machine where encoding="one_hot": pcie_drx.vhd:137:11:
> > no declaration for "enum_encoding"
> >
> > I can resolve ghdl's complaints by adding attribute enum_encoding:
> > string; to the generated .vhd file.
> >
> > Is there a way to have this line included automatically in .vhd
> > output? I could add it via a shell script, but I'm wondering if
> > there is "better way" to do it. (or is GHDL in error?)
> >
> >
> > For example, here is an trimmed-down excerpt from the top of the .vhd
> > file showing where I add the line:
> >
> > package pck_pcie_drx is attribute enum_encoding: string; <--- I need
> > to add this line.
> >
> > type t_enum_t_state_22 is (
> >
> > IDLE,
> >
> > THINK,
> >
> > SEND_CMD,
> >
> > ADVANCE
> >
> > );
> >
> > attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100
> > 1000";
> >
> > type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2,
> > MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding
> > of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000
> > 00010000 00100000 01000000 10000000"; end package pck_pcie_drx;
> > library IEEE; etc...
> >
> >
> >
> >
> > - David ps: Thank you for the fantastic MyHDL.
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> >
> >
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> > Discover the easy way to master current and previous Microsoft
> > technologies and advance your career. Get an incredible 1,500+ hours
> > of step-by-step tutorial videos with LearnDevNow. Subscribe today and
> > save!
> >
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
> >
> >
> >
> >
> > _______________________________________________ myhdl-list mailing
> > list myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Python as a HDL: http://www.myhdl.org
> VHDL development, the modern way: http://www.sigasi.com
> World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
|
|
From: Jan D. <ja...@ja...> - 2013-09-10 10:28:35
|
Mm, I suspect there will still be a bug iff an enum type is used at the top-level. If someone provides a failing test case, I'll fix it :-) On 09/09/2013 02:43 PM, David Holl wrote: > ugh! My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012. Updating to the latest 0.8 fixed the problem. > > The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;" > > package pck_pcie_drx is > type t_enum_t_state_1 is ( > SM_RESET, > ... > > (but my design does not use any enum's in the ports) > > However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.numeric_std.all; > use std.textio.all; > use work.pck_myhdl_08.all; > entity pcie_drx is > port ( > user_clk: in std_logic; > ... > > > Thank you Chris and Jan for looking into this! > - David > > > On Mon, Sep 9, 2013 at 6:25 AM, Jan Decaluwe <ja...@ja... <mailto:ja...@ja...>> wrote: > > Mm, the attribute is declared in pck_myhdl but probably this > is namespace issue. Iff a port uses an enum, then a top-level > package is needed and the declaration is not seen, unlike > when the enum type is declared in the architecture. > > Jan > > On 09/03/2013 09:48 PM, David Holl wrote: > > Hello, When using ghdl for syntax checks, I get the following error > > for any state machine where encoding="one_hot": pcie_drx.vhd:137:11: > > no declaration for "enum_encoding" > > > > I can resolve ghdl's complaints by adding attribute enum_encoding: > > string; to the generated .vhd file. > > > > Is there a way to have this line included automatically in .vhd > > output? I could add it via a shell script, but I'm wondering if > > there is "better way" to do it. (or is GHDL in error?) > > > > > > For example, here is an trimmed-down excerpt from the top of the .vhd > > file showing where I add the line: > > > > package pck_pcie_drx is attribute enum_encoding: string; <--- I need > > to add this line. > > > > type t_enum_t_state_22 is ( > > > > IDLE, > > > > THINK, > > > > SEND_CMD, > > > > ADVANCE > > > > ); > > > > attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100 > > 1000"; > > > > type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2, > > MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding > > of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000 > > 00010000 00100000 01000000 10000000"; end package pck_pcie_drx; > > library IEEE; etc... > > > > > > > > > > - David ps: Thank you for the fantastic MyHDL. > > > > > > > > ------------------------------------------------------------------------------ > > > > > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > > Discover the easy way to master current and previous Microsoft > > technologies and advance your career. Get an incredible 1,500+ hours > > of step-by-step tutorial videos with LearnDevNow. Subscribe today and > > save! > > http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk > > > > > > > > > > _______________________________________________ myhdl-list mailing > > list myh...@li... <mailto:myh...@li...> > > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > -- > Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com > Python as a HDL: http://www.myhdl.org > VHDL development, the modern way: http://www.sigasi.com > World-class digital design: http://www.easics.com > > ------------------------------------------------------------------------------ > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > Discover the easy way to master current and previous Microsoft technologies > and advance your career. Get an incredible 1,500+ hours of step-by-step > tutorial videos with LearnDevNow. Subscribe today and save! > http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk > _______________________________________________ > myhdl-list mailing list > myh...@li... <mailto:myh...@li...> > https://lists.sourceforge.net/lists/listinfo/myhdl-list > > > > > ------------------------------------------------------------------------------ > Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more! > Discover the easy way to master current and previous Microsoft technologies > and advance your career. Get an incredible 1,500+ hours of step-by-step > tutorial videos with LearnDevNow. Subscribe today and save! > http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
|
From: David H. <da...@ad...> - 2013-09-12 06:19:40
Attachments:
signature.asc
test_enum_toVHDL.py
|
On Tue, Sep 10, 2013 at 12:28:25PM +0200, Jan Decaluwe wrote:
> Mm, I suspect there will still be a bug iff an
> enum type is used at the top-level.
>
> If someone provides a failing test case, I'll
> fix it :-)
Wish granted. :) I've attached a test that fails on MyHDL 0.8. Pardon the
contrived example; I lobotomized a perfectly functioning state machine to
achieve using a top-level enum. (reduced to 2 states, removed PCIe junk...)
It passes toVerilog and conversion.analyze (with .simulator='icarus').
But it will fail during toVHDL, or if you comment out the toVHDL test, it will
also fail during conversion.analyze (.simulator='GHDL') with this error:
subspace(ttys003):~> python test_enum_toVHDL.py
Analysis succeeded <-- This message is after passing toVerilog & icarus
Traceback (most recent call last):
File "test_enum_toVHDL.py", line 48, in <module>
toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert)
File "/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/conversion/_toVHDL.py", line 173, in __call__
assert obj in _enumTypeSet
AssertionError <-- This is upon trying either toVHDL or ghdl analysis.
- David
>
> On 09/09/2013 02:43 PM, David Holl wrote:
> > ugh! My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012. Updating to the latest 0.8 fixed the problem.
> >
> > The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;"
> >
> > package pck_pcie_drx is
> > type t_enum_t_state_1 is (
> > SM_RESET,
> > ...
> >
> > (but my design does not use any enum's in the ports)
> >
> > However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with
> >
> > library IEEE;
> > use IEEE.std_logic_1164.all;
> > use IEEE.numeric_std.all;
> > use std.textio.all;
> > use work.pck_myhdl_08.all;
> > entity pcie_drx is
> > port (
> > user_clk: in std_logic;
> > ...
> >
> >
> > Thank you Chris and Jan for looking into this!
> > - David
|
|
From: Jan D. <ja...@ja...> - 2013-09-13 22:21:28
|
Mm, this fails on toVHDL() already, regardless of the encoding ... something else is wrong here. On 09/12/2013 08:19 AM, David Holl wrote: > On Tue, Sep 10, 2013 at 12:28:25PM +0200, Jan Decaluwe wrote: >> Mm, I suspect there will still be a bug iff an >> enum type is used at the top-level. >> >> If someone provides a failing test case, I'll >> fix it :-) > > Wish granted. :) I've attached a test that fails on MyHDL 0.8. Pardon the > contrived example; I lobotomized a perfectly functioning state machine to > achieve using a top-level enum. (reduced to 2 states, removed PCIe junk...) > > It passes toVerilog and conversion.analyze (with .simulator='icarus'). > > But it will fail during toVHDL, or if you comment out the toVHDL test, it will > also fail during conversion.analyze (.simulator='GHDL') with this error: > > > subspace(ttys003):~> python test_enum_toVHDL.py > Analysis succeeded <-- This message is after passing toVerilog & icarus > Traceback (most recent call last): > File "test_enum_toVHDL.py", line 48, in <module> > toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) > File "/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/conversion/_toVHDL.py", line 173, in __call__ > assert obj in _enumTypeSet > AssertionError <-- This is upon trying either toVHDL or ghdl analysis. > > > - David > > >> >> On 09/09/2013 02:43 PM, David Holl wrote: >>> ugh! My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012. Updating to the latest 0.8 fixed the problem. >>> >>> The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;" >>> >>> package pck_pcie_drx is >>> type t_enum_t_state_1 is ( >>> SM_RESET, >>> ... >>> >>> (but my design does not use any enum's in the ports) >>> >>> However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with >>> >>> library IEEE; >>> use IEEE.std_logic_1164.all; >>> use IEEE.numeric_std.all; >>> use std.textio.all; >>> use work.pck_myhdl_08.all; >>> entity pcie_drx is >>> port ( >>> user_clk: in std_logic; >>> ... >>> >>> >>> Thank you Chris and Jan for looking into this! >>> - David >>> >>> >>> ------------------------------------------------------------------------------ >>> How ServiceNow helps IT people transform IT departments: >>> 1. Consolidate legacy IT systems to a single system of record for IT >>> 2. Standardize and globalize service processes across IT >>> 3. Implement zero-touch automation to replace manual, redundant tasks >>> http://pubads.g.doubleclick.net/gampad/clk?id=51271111&iu=/4140/ostg.clktrk >>> >>> >>> _______________________________________________ >>> myhdl-list mailing list >>> myh...@li... >>> https://lists.sourceforge.net/lists/listinfo/myhdl-list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
|
From: Jan D. <ja...@ja...> - 2013-09-20 16:17:01
|
These issues have been fixed in development. On 09/12/2013 08:19 AM, David Holl wrote: > On Tue, Sep 10, 2013 at 12:28:25PM +0200, Jan Decaluwe wrote: >> Mm, I suspect there will still be a bug iff an >> enum type is used at the top-level. >> >> If someone provides a failing test case, I'll >> fix it :-) > > Wish granted. :) I've attached a test that fails on MyHDL 0.8. Pardon the > contrived example; I lobotomized a perfectly functioning state machine to > achieve using a top-level enum. (reduced to 2 states, removed PCIe junk...) > > It passes toVerilog and conversion.analyze (with .simulator='icarus'). > > But it will fail during toVHDL, or if you comment out the toVHDL test, it will > also fail during conversion.analyze (.simulator='GHDL') with this error: > > > subspace(ttys003):~> python test_enum_toVHDL.py > Analysis succeeded <-- This message is after passing toVerilog & icarus > Traceback (most recent call last): > File "test_enum_toVHDL.py", line 48, in <module> > toVHDL(pcie_legacyint_next_state_logic, state, next_state, next_state_en, interrupt_pending, interrupt_assert) > File "/Users/dholl/Library/Python/2.7/lib/python/site-packages/myhdl/conversion/_toVHDL.py", line 173, in __call__ > assert obj in _enumTypeSet > AssertionError <-- This is upon trying either toVHDL or ghdl analysis. > > > - David > > >> >> On 09/09/2013 02:43 PM, David Holl wrote: >>> ugh! My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012. Updating to the latest 0.8 fixed the problem. >>> >>> The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;" >>> >>> package pck_pcie_drx is >>> type t_enum_t_state_1 is ( >>> SM_RESET, >>> ... >>> >>> (but my design does not use any enum's in the ports) >>> >>> However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with >>> >>> library IEEE; >>> use IEEE.std_logic_1164.all; >>> use IEEE.numeric_std.all; >>> use std.textio.all; >>> use work.pck_myhdl_08.all; >>> entity pcie_drx is >>> port ( >>> user_clk: in std_logic; >>> ... >>> >>> >>> Thank you Chris and Jan for looking into this! >>> - David >>> >>> >>> ------------------------------------------------------------------------------ >>> How ServiceNow helps IT people transform IT departments: >>> 1. Consolidate legacy IT systems to a single system of record for IT >>> 2. Standardize and globalize service processes across IT >>> 3. Implement zero-touch automation to replace manual, redundant tasks >>> http://pubads.g.doubleclick.net/gampad/clk?id=51271111&iu=/4140/ostg.clktrk >>> >>> >>> _______________________________________________ >>> myhdl-list mailing list >>> myh...@li... >>> https://lists.sourceforge.net/lists/listinfo/myhdl-list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
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