Thread: [myhdl-list] Proposal: New class, ClockDomain
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From: Keerthan jai.c <jck...@gm...> - 2013-05-15 00:22:54
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Do you think it is a good idea to have a new class ClockDoman, which
contains a clock and reset signal? Typically, we use the same clock and
reset signals for most modules, having a clock domain object might simplify
this.
Example:
def module(cd, ports...):
@always_seq(cd)
....
clk = Signal(bool(0))
rst = ResetSignal(1, active=0, async=True)
app_clk = ClockDomain(clk, rst)
inst = module(app_clk, ports..
--
have a nice day
-jck
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From: Christopher F. <chr...@gm...> - 2013-05-15 00:42:37
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On 5/14/13 7:22 PM, Keerthan jai.c wrote:
> Do you think it is a good idea to have a new class ClockDoman, which
> contains a clock and reset signal? Typically, we use the same clock and
> reset signals for most modules, having a clock domain object might
> simplify this.
>
> Example:
> def module(cd, ports...):
> @always_seq(cd)
> ....
>
> clk = Signal(bool(0))
> rst = ResetSignal(1, active=0, async=True)
> app_clk = ClockDomain(clk, rst)
>
> inst = module(app_clk, ports..
>
>
> --
> have a nice day
> -jck
>
>
I think this is too application specific to be
included in the base myhdl pkg. It is fairly
light to include:
class SystemSignals:
def __init__(def, frequency=1):
self.clock = Signal(bool(0))
self.reset = ResetSignal(0,active=0,async=False)
def m_sync_reset(ext_reset, reset)
...
def m_some_module(syssigs, *ports):
clock = syssigs.clock
reset = syssigs.reset
...
def m_some_top(...):
domain1 = SystemSignals(frequency=50e6)
domain2 = SystemSignals(frequency=333e6)
g_rst1 = domain1.m_sync_reset(ext_reset, domain1.reset)
g_rst2 = domain2.m_sync_reset(ext_reset, domain2.reset)
g1 = m_some_module(domain1, ...)
g2 = m_some_module(domain2, ...)
...
in an project. Sorry, I like to type out /clock/
and /reset/ :)
Regards,
Chris
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From: Christopher L. <loz...@fr...> - 2013-05-15 01:47:46
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Clock domain is a great idea. There should be a rich and interesting library of Hardware modules available as a library in MyHDL. It makes life so much easier for the Newbies. Sure it is not that much code for the experienced guys to write one class, but it has to do with mindsets. As an experienced object oriented developer new to MyHDL, I expect a rich and interesting class library to exist and be available for reuse. Here is one such suggested library. http://www.oohdl.com/HarwareModuleClassLibrary Then I could make a blinking light out of a clock, and a counter. Just watch the 22nd bit on the counter, to see it blink at human speed. http://www.oohdl.com/Blinking_Light Much better than writing it from scratch. The fact that such a library does not exist, that it is discouraged, that there is no culture of publishing and sharing class libraries in MyHDL gives me pause. Perhaps it is more efficient to write things from scratch, but for us newbies, it is way way easier to reuse existing class libraries. -- I run http://Django.SpecialtyJobMarkets.com Regards Christopher Lozinski The future of Zope http://ZOPACHE.COM On Digital Design http://OOHDL.COM |
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From: Jan D. <ja...@ja...> - 2013-05-15 07:32:23
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On 05/15/2013 03:47 AM, Christopher Lozinski wrote: > Clock domain is a great idea. > > There should be a rich and interesting library of Hardware modules > available as a library in MyHDL. > > It makes life so much easier for the Newbies. > > Sure it is not that much code for the experienced guys to write one > class, but it has to do with mindsets. As an experienced object > oriented developer > new to MyHDL, I expect a rich and interesting class library to exist and > be available for reuse. > > Here is one such suggested library. > > http://www.oohdl.com/HarwareModuleClassLibrary BTW - I hate that classification - way too much level. Not useful for real HDL work. > Then I could make a blinking light out of a clock, and a counter. > Just watch the 22nd bit on the counter, to see it blink at human speed. > > http://www.oohdl.com/Blinking_Light > > Much better than writing it from scratch. > > The fact that such a library does not exist, that it is discouraged, > that there is no culture of publishing and sharing class libraries in > MyHDL gives me pause. > > Perhaps it is more efficient to write things from scratch, but for us > newbies, it is way way easier to reuse existing class libraries. > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
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From: Jan D. <ja...@ja...> - 2013-05-15 07:11:59
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On 05/15/2013 02:22 AM, Keerthan jai.c wrote: > Do you think it is a good idea to have a new class ClockDoman, Not in the myhdl library itself, and not enough value to support for conversion. which contains a clock and reset signal? Typically, we use the same clock and reset signals for most modules, having a clock domain object might simplify this. > > Example: > def module(cd, ports...): > @always_seq(cd) > .... > > clk = Signal(bool(0)) > rst = ResetSignal(1, active=0, async=True) > app_clk = ClockDomain(clk, rst) > > inst = module(app_clk, ports.. > > > -- > have a nice day > -jck > > > ------------------------------------------------------------------------------ > AlienVault Unified Security Management (USM) platform delivers complete > security visibility with the essential security capabilities. Easily and > efficiently configure, manage, and operate all of your security controls > from a single console and one unified framework. Download a free trial. > http://p.sf.net/sfu/alienvault_d2d > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
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From: Jan D. <ja...@ja...> - 2013-05-15 07:29:23
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On 05/15/2013 03:47 AM, Christopher Lozinski wrote: > Clock domain is a great idea. > > There should be a rich and interesting library of Hardware modules > available as a library in MyHDL. Of course there should not. Unlike Python, it is totally unclear how a "standard" library for MyHDL should look like. Guido himself recently explained how the concept of the Python standard library is frequently misunderstood. The Python standard library is like a minimum set of generally useful functionality, on which there is basically a consensus. However, being in the standard library is not a blessing. It takes ages, and you have comply with all kinds of Python-release related restrictions. I certainly would not want MyHDL to be in the Python standard library. For innovation, you don't want a standard library. For the record, I am of course all of for "rich and interesting libraries of MyHDL hardware modules" - plenty of them, including competing ones. Just do not look at me or the MyHDL library itself for that - I am doing my share and I have many other plans. Nothing prevents you or anyone to make your hands dirty and start with it today. Let's stop the high-level talk and get to work. -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com World-class digital design: http://www.easics.com |
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From: Oscar D. D. <osc...@gm...> - 2013-05-17 17:35:45
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El Wed, 15 May 2013 09:29:15 +0200 Jan Decaluwe <ja...@ja...> escribió: > On 05/15/2013 03:47 AM, Christopher Lozinski wrote: > > Clock domain is a great idea. > > > > There should be a rich and interesting library of Hardware modules > > available as a library in MyHDL. > > Of course there should not. > > Unlike Python, it is totally unclear how a "standard" library for > MyHDL should look like. > > Guido himself recently explained how the concept of the Python > standard library is frequently misunderstood. The Python standard > library is like a minimum set of generally useful functionality, > on which there is basically a consensus. > > However, being in the standard library is not a blessing. It takes > ages, and you have comply with all kinds of Python-release related > restrictions. I certainly would not want MyHDL to be in the > Python standard library. For innovation, you don't want a > standard library. > > For the record, I am of course all of for "rich and interesting > libraries of MyHDL hardware modules" - plenty of them, including > competing ones. Just do not look at me or the MyHDL library itself for > that - I am doing my share and I have many other plans. Totally agree. Lately I though about how to gather different contributions into one (or several) modules. I was thinking on making a module index on the wiki; with module descriptions and some search keywords. The current mechanism is the user's pages and its own descriptions of their projects. Also, I think we should define some coding guidelines for the modules to be included on the index, so we have basic quality standard. Another option is to use bitbucket features for group develop, I'm checking what bitbucket offers for multi-users. > > Nothing prevents you or anyone to make your hands dirty and > start with it today. Let's stop the high-level talk and get > to work. > Best regards, -- Oscar Díaz Key Fingerprint = 904B 306C C3C2 7487 650B BFAC EDA2 B702 90E9 9964 gpg --keyserver subkeys.pgp.net --recv-keys 90E99964 I recommend using OpenDocument Format for daily use and exchange of documents. http://www.fsf.org/campaigns/opendocument |
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From: Christopher L. <loz...@fr...> - 2013-05-17 18:10:14
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On 5/17/13 12:23 PM, Oscar Daniel Diaz wrote: > I was thinking on making a module index on the wiki; with module > descriptions and some search keywords. The current mechanism is the > user's pages and its own descriptions of their projects. That is a great idea. There are probably more classes available than any one of us know about. And they are all over the place, git, mercurial, tarballs. It just needs a brief high level description, and a link to the source code for more information. A pypi link if they are using that distribution method. Or a link to the home page for the product, or article. Of course the ability to rate modules would be great. Dependencies would be great. But at least a listing of hardware modules would be a start. You can start with a brief description of the classes you wrote, and a link to their location, and to the article you wrote. -- I run http://Django.SpecialtyJobMarkets.com Regards Christopher Lozinski The future of Zope http://ZOPACHE.COM On Digital Design http://OOHDL.COM |
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From: Christopher F. <chr...@gm...> - 2013-05-17 18:07:51
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On 5/17/13 12:23 PM, Oscar Daniel Diaz wrote: > El Wed, 15 May 2013 09:29:15 +0200 > Jan Decaluwe <ja...@ja...> escribió: > >> On 05/15/2013 03:47 AM, Christopher Lozinski wrote: >>> Clock domain is a great idea. >>> >>> There should be a rich and interesting library of Hardware modules >>> available as a library in MyHDL. >> >> Of course there should not. >> >> Unlike Python, it is totally unclear how a "standard" library for >> MyHDL should look like. >> >> Guido himself recently explained how the concept of the Python >> standard library is frequently misunderstood. The Python standard >> library is like a minimum set of generally useful functionality, >> on which there is basically a consensus. >> >> However, being in the standard library is not a blessing. It takes >> ages, and you have comply with all kinds of Python-release related >> restrictions. I certainly would not want MyHDL to be in the >> Python standard library. For innovation, you don't want a >> standard library. >> >> For the record, I am of course all of for "rich and interesting >> libraries of MyHDL hardware modules" - plenty of them, including >> competing ones. Just do not look at me or the MyHDL library itself for >> that - I am doing my share and I have many other plans. > > Totally agree. Lately I though about how to gather different > contributions into one (or several) modules. > > I was thinking on making a module index on the wiki; with module > descriptions and some search keywords. The current mechanism is the > user's pages and its own descriptions of their projects. There is a little bit of this in the user-space, but to have a dedicated page with a module link and short description and, maybe, a few checkboxes like open-cores (model, convertible, ect) would be an straightforward way to get going. There have been a few useful modules posted to the mailing-list (I think only exist on the mailing list). > > Also, I think we should define some coding guidelines for the modules > to be included on the index, so we have basic quality standard. There has been past discussions if it would be possible to create an open-cores like site with a bunch of myhdl modules. If you have a site with this goal you can have guidelines etc (I would like to see complete tests more than syntax guidelines as a requirement). But you would need someone fairly dedicated to build the site. > > Another option is to use bitbucket features for group develop, I'm > checking what bitbucket offers for multi-users. You can look at other projects like pypy hosted on bitbucket, bitbucket does have "groups", I think this is a simple way to control permissions/access. Example, you could create a group, /myhdl_cores/ (or whatever) and have myhdl_cores_public repository that you give permissions to a large group. The documentation for the cores can be in sphinx and you can post/host it on "readthedocs". It would be useful/interesting to have nightly builds where the cores are checked for changes and if so the tests are run against the cores. You can have a real-time status of which cores are stable (ish). But it is easy to talk about this stuff and throw some ideas around but it is some work to actually put it all together. I would be supportive and could move a bunch of my stuff to the repo, if one was put together and it looked promising. Regards, Chris |
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From: Oscar D. D. <osc...@gm...> - 2013-05-20 23:32:44
Attachments:
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El Fri, 17 May 2013 13:07:30 -0500 Christopher Felton <chr...@gm...> escribió: > > I was thinking on making a module index on the wiki; with module > > descriptions and some search keywords. The current mechanism is the > > user's pages and its own descriptions of their projects. > > There is a little bit of this in the user-space, but to have > a dedicated page with a module link and short description > and, maybe, a few checkboxes like open-cores (model, > convertible, ect) would be an straightforward way to get > going. There have been a few useful modules posted to > the mailing-list (I think only exist on the mailing list). > > > > > Also, I think we should define some coding guidelines for the > > modules to be included on the index, so we have basic quality > > standard. > > There has been past discussions if it would be possible > to create an open-cores like site with a bunch of myhdl > modules. If you have a site with this goal you can have > guidelines etc (I would like to see complete tests more > than syntax guidelines as a requirement). But you would > need someone fairly dedicated to build the site. Fair enough, but I think we can all contribute to build this "page" in a wiki way, at least at beginning. > > Another option is to use bitbucket features for group develop, I'm > > checking what bitbucket offers for multi-users. > > You can look at other projects like pypy hosted on bitbucket, > bitbucket does have "groups", I think this is a simple way > to control permissions/access. Example, you could create > a group, /myhdl_cores/ (or whatever) and have myhdl_cores_public > repository that you give permissions to a large group. I checked bitbucket groups: that's a very nice way for group development. > The documentation for the cores can be in sphinx and you can > post/host it on "readthedocs". It would be useful/interesting > to have nightly builds where the cores are checked for changes > and if so the tests are run against the cores. You can have a > real-time status of which cores are stable (ish). > > But it is easy to talk about this stuff and throw some ideas > around but it is some work to actually put it all together. I > would be supportive and could move a bunch of my stuff to the > repo, if one was put together and it looked promising. Fair enough. Right now I'm working on a library for wishbone and AXI4 bus support (I'm still working on the test and documentation), and of course I'll use bitbucket. What I propose is: * Start with a bitbucket repo * Comply with guidelines (for example, require documentation and test suites) * Add an entry to the index wiki * If someone wants to contribute with that particular module, use bitbucket groups. I'm planing to write a guideline draft and an index template. But let me check Sphinx first. Best regards, -- Oscar Díaz Key Fingerprint = 904B 306C C3C2 7487 650B BFAC EDA2 B702 90E9 9964 gpg --keyserver subkeys.pgp.net --recv-keys 90E99964 I recommend using OpenDocument Format for daily use and exchange of documents. http://www.fsf.org/campaigns/opendocument |
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From: Christopher F. <chr...@gm...> - 2013-05-22 14:13:03
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On 5/20/2013 6:30 PM, Oscar Daniel Diaz wrote: > El Fri, 17 May 2013 13:07:30 -0500 > Christopher Felton <chr...@gm...> escribió: > >>> I was thinking on making a module index on the wiki; with module >>> descriptions and some search keywords. The current mechanism is the >>> user's pages and its own descriptions of their projects. >> >> There is a little bit of this in the user-space, but to have >> a dedicated page with a module link and short description >> and, maybe, a few checkboxes like open-cores (model, >> convertible, ect) would be an straightforward way to get >> going. There have been a few useful modules posted to >> the mailing-list (I think only exist on the mailing list). >> >>> >>> Also, I think we should define some coding guidelines for the >>> modules to be included on the index, so we have basic quality >>> standard. >> >> There has been past discussions if it would be possible >> to create an open-cores like site with a bunch of myhdl >> modules. If you have a site with this goal you can have >> guidelines etc (I would like to see complete tests more >> than syntax guidelines as a requirement). But you would >> need someone fairly dedicated to build the site. > > Fair enough, but I think we can all contribute to build this "page" in > a wiki way, at least at beginning. > I agree the wiki page is an easy way to get going. <snip> >> But it is easy to talk about this stuff and throw some ideas >> around but it is some work to actually put it all together. I >> would be supportive and could move a bunch of my stuff to the >> repo, if one was put together and it looked promising. > > Fair enough. Right now I'm working on a library for wishbone and AXI4 > bus support (I'm still working on the test and documentation), and of > course I'll use bitbucket. What I propose is: > > * Start with a bitbucket repo > * Comply with guidelines (for example, require documentation and test > suites) > * Add an entry to the index wiki > * If someone wants to contribute with that particular module, use > bitbucket groups. > > I'm planing to write a guideline draft and an index template. But let > me check Sphinx first. > > Best regards, > This is something I think could benefit from some lively conversation and experimentation. I have gone down this path a bunch of time and posted examples. I have implemented various control buses (i.e. mem-map buses) for different projects. In my mind we should be able to come up with a very elegant control bus interface which includes a flexible method to define the register file for each component on the control bus. Regards, Chris |
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From: Oscar D. D. <osc...@gm...> - 2013-05-22 15:37:42
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El Wed, 22 May 2013 09:12:43 -0500 Christopher Felton <chr...@gm...> escribió: > <snip> > >> But it is easy to talk about this stuff and throw some ideas > >> around but it is some work to actually put it all together. I > >> would be supportive and could move a bunch of my stuff to the > >> repo, if one was put together and it looked promising. > > > > Fair enough. Right now I'm working on a library for wishbone and > > AXI4 bus support (I'm still working on the test and documentation), > > and of course I'll use bitbucket. What I propose is: > > > > * Start with a bitbucket repo > > * Comply with guidelines (for example, require documentation and > > test suites) > > * Add an entry to the index wiki > > * If someone wants to contribute with that particular module, use > > bitbucket groups. > > > > I'm planing to write a guideline draft and an index template. But > > let me check Sphinx first. > > > > Best regards, > > > > This is something I think could benefit from some lively > conversation and experimentation. I have gone down this > path a bunch of time and posted examples. I have implemented > various control buses (i.e. mem-map buses) for different > projects. In my mind we should be able to come up with a > very elegant control bus interface which includes a flexible > method to define the register file for each component on the > control bus. I guess some of us were working on the same issues on our projects; that's another motivation for the index and group develop. I proposed my bus library initially as a "test" for this procedure, but I also want it to be a useful library. In fact, I have a lot of clean-up and re-factor to do, so I'd be glad to hear feedback about it. By the way I forgot the link in the previous email: https://bitbucket.org/dargor0/myhdl_buslib > > Regards, > Chris > > > > > ------------------------------------------------------------------------------ > Try New Relic Now & We'll Send You this Cool Shirt > New Relic is the only SaaS-based application performance monitoring > service that delivers powerful full stack analytics. Optimize and > monitor your browser, app, & servers with just a few lines of code. > Try New Relic and get this awesome Nerd Life shirt! > http://p.sf.net/sfu/newrelic_d2d_may > _______________________________________________ myhdl-list mailing > list myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list Best regards, -- Oscar Díaz Key Fingerprint = 904B 306C C3C2 7487 650B BFAC EDA2 B702 90E9 9964 gpg --keyserver subkeys.pgp.net --recv-keys 90E99964 I recommend using OpenDocument Format for daily use and exchange of documents. http://www.fsf.org/campaigns/opendocument |
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From: Christopher F. <chr...@gm...> - 2013-05-22 16:21:00
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<snip> >> >> This is something I think could benefit from some lively >> conversation and experimentation. I have gone down this >> path a bunch of time and posted examples. I have implemented >> various control buses (i.e. mem-map buses) for different >> projects. In my mind we should be able to come up with a >> very elegant control bus interface which includes a flexible >> method to define the register file for each component on the >> control bus. > > I guess some of us were working on the same issues on our projects; > that's another motivation for the index and group develop. > > I proposed my bus library initially as a "test" for this procedure, > but I also want it to be a useful library. In fact, I have a lot of > clean-up and re-factor to do, so I'd be glad to hear feedback about > it. > > By the way I forgot the link in the previous email: > > https://bitbucket.org/dargor0/myhdl_buslib > Here is an example I tried to put together, never quite finished. I was hoping this would be an example for the interface efforts we have been discussing. https://bitbucket.org/cfelton/examples/src/tip/simple It will be a couple days before I can review your code and contrast it the above example. Regards, Chris |
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