Thread: [myhdl-list] Function calls in combinatorial blocks
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From: Per K. <bas...@gm...> - 2013-03-01 20:41:22
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Hi! Is there a particular reason that we do not support function calls in combinatorial blocks? In 0.7 I get: File "[...]_analyze.py", line 165, in _analyzeGens _isMem(obj) or _isTupleOfInts(obj) In 0.8dev I get: File "[...]_analyze.py", line 168, in _analyzeGens raise ConversionError(_error.UnsupportedType, n, info) myhdl.ConversionError: File file.py, line 11: Object type is not supported in this context: f Here is a test snippet: ######################### from myhdl import * def w(a, b, c, clk): def f(a): out = intbv(0)[len(a):] if a<3: out[:] = a else: out[:] = 0 return out @always_comb def cm(): b.next = a @always(clk.posedge) def ck(): c.next = f(a) return instances() def test(): a = Signal(intbv(0)[10:]) b = Signal(intbv(0)[10:]) c = Signal(intbv(0)[10:]) clk = Signal(bool(0)) dut = toVerilog(w, a, b,c ,clk) return instances() s = Simulation(test()) s.run() ########################## -Cheers! /Per |
From: Christopher F. <chr...@gm...> - 2013-03-01 21:16:58
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On 3/1/2013 9:12 AM, Per Karlsson wrote: > Hi! > Is there a particular reason that we do not support function calls in > combinatorial blocks? > I don't know if there is a reason, my guess is not. But it is currently *not* supported. To have the feature added it is ideal to create a MEP describing the feature. Can simply start by describing the enhancement request to the mailing-list. My opinion, there are two levels: modeling and conversion. In some cases we might want to take baby steps to implement, first just add for modeling and then for conversion. Regards, Chris |
From: Christopher F. <chr...@gm...> - 2013-03-02 13:11:44
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On 3/1/13 3:16 PM, Christopher Felton wrote: > On 3/1/2013 9:12 AM, Per Karlsson wrote: >> Hi! >> Is there a particular reason that we do not support function calls in >> combinatorial blocks? >> > > I don't know if there is a reason, my guess is > not. But it is currently *not* supported. To > have the feature added it is ideal to create a > MEP describing the feature. Can simply start > by describing the enhancement request to the > mailing-list. > > My opinion, there are two levels: modeling and > conversion. In some cases we might want to take > baby steps to implement, first just add for modeling > and then for conversion. I should clarify, this works for "modeling" you can have a function on the right hand side, I was speaking generally in the second paragraph. Best of my knowledge, functions as described (on the RHS of and assignment) are not convertible but I don't see why we can't create a MEP and add it to the list of future features. Regards, Chris |
From: Christopher F. <chr...@gm...> - 2013-04-02 13:43:25
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On 3/2/2013 7:11 AM, Christopher Felton wrote: > On 3/1/13 3:16 PM, Christopher Felton wrote: >> On 3/1/2013 9:12 AM, Per Karlsson wrote: >>> Hi! >>> Is there a particular reason that we do not support function calls in >>> combinatorial blocks? >>> >> >> I don't know if there is a reason, my guess is >> not. But it is currently *not* supported. To >> have the feature added it is ideal to create a >> MEP describing the feature. Can simply start >> by describing the enhancement request to the >> mailing-list. >> >> My opinion, there are two levels: modeling and >> conversion. In some cases we might want to take >> baby steps to implement, first just add for modeling >> and then for conversion. > > I should clarify, this works for "modeling" you can > have a function on the right hand side, I was speaking > generally in the second paragraph. > > Best of my knowledge, functions as described (on the RHS > of and assignment) are not convertible but I don't see > why we can't create a MEP and add it to the list of > future features. > > Regards, > Chris > > Hmmm, not sure what happened when I replied to this thread awhile ago. I (*thought*) I tested this and saw the same phenomenon and thought it was not a supported feature. Yet again, I was *wrong*! (a new post reminded me) A function in an /always_comb/ should be supported. I included an example below. If you have an example that is not working let us know and I will see if I can help. Sorry about any confusion. Regards, Chris ~~~ [Example with functions on RHS] ~~~~ def cadd(a,b): return a + b def m_add_seq(clock,reset,a,b,c): @always_seq(clock.posedge, reset=reset) def hdl(): c.next = cadd(a,b) return hdl def m_add_comb(a,b,c): @always_comb def hdl(): c.next = cadd(a,b) return hdl def test_add(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) a,b = [Signal(intbv(0,min=-4,max=4)) for ii in (0,1)] cs = Signal(intbv(0,min=-8,max=8)) cc = Signal(intbv(0,min=-8,max=8)) @always(delay(3)) def tb_clock(): clock.next = not clock tb_dut_s = m_add_seq(clock,reset,a,b,cs) tb_dut_c = m_add_comb(a,b,cc) @instance def tb_stim(): reset.next = False yield delay(10) reset.next = True yield delay(10) yield clock.posedge for aa in xrange(4): for bb in xrange(4): a.next = aa b.next = bb yield clock.posedge yield clock.posedge assert cs == (a+b) assert cc == (a+b) raise StopSimulation Simulation((tb_clock,tb_dut_s,tb_dut_c,tb_stim)).run() toVerilog(m_add_seq,clock,reset,a,b,cs) toVerilog(m_add_comb,a,b,cc) |
From: Per K. <bas...@gm...> - 2013-04-02 15:17:57
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There was an example in my original post. But of course there may be something else that's wrong with that. Especially since I just tried your example... and it works! :) /Per On Tue, Apr 2, 2013 at 3:42 PM, Christopher Felton <chr...@gm...>wrote: > On 3/2/2013 7:11 AM, Christopher Felton wrote: > > On 3/1/13 3:16 PM, Christopher Felton wrote: > >> On 3/1/2013 9:12 AM, Per Karlsson wrote: > >>> Hi! > >>> Is there a particular reason that we do not support function calls in > >>> combinatorial blocks? > >>> > >> > >> I don't know if there is a reason, my guess is > >> not. But it is currently *not* supported. To > >> have the feature added it is ideal to create a > >> MEP describing the feature. Can simply start > >> by describing the enhancement request to the > >> mailing-list. > >> > >> My opinion, there are two levels: modeling and > >> conversion. In some cases we might want to take > >> baby steps to implement, first just add for modeling > >> and then for conversion. > > > > I should clarify, this works for "modeling" you can > > have a function on the right hand side, I was speaking > > generally in the second paragraph. > > > > Best of my knowledge, functions as described (on the RHS > > of and assignment) are not convertible but I don't see > > why we can't create a MEP and add it to the list of > > future features. > > > > Regards, > > Chris > > > > > > Hmmm, not sure what happened when I replied to this > thread awhile ago. I (*thought*) I tested this and > saw the same phenomenon and thought it was not a > supported feature. Yet again, I was *wrong*! > (a new post reminded me) > > A function in an /always_comb/ should be supported. > I included an example below. If you have an example > that is not working let us know and I will see if > I can help. Sorry about any confusion. > > Regards, > Chris > > > ~~~ [Example with functions on RHS] ~~~~ > > def cadd(a,b): > return a + b > > def m_add_seq(clock,reset,a,b,c): > @always_seq(clock.posedge, reset=reset) > def hdl(): > c.next = cadd(a,b) > return hdl > > def m_add_comb(a,b,c): > @always_comb > def hdl(): > c.next = cadd(a,b) > return hdl > > def test_add(): > clock = Signal(bool(0)) > reset = ResetSignal(0, active=0, async=False) > a,b = [Signal(intbv(0,min=-4,max=4)) for ii in (0,1)] > cs = Signal(intbv(0,min=-8,max=8)) > cc = Signal(intbv(0,min=-8,max=8)) > > @always(delay(3)) > def tb_clock(): > clock.next = not clock > > tb_dut_s = m_add_seq(clock,reset,a,b,cs) > tb_dut_c = m_add_comb(a,b,cc) > > @instance > def tb_stim(): > reset.next = False > yield delay(10) > reset.next = True > yield delay(10) > yield clock.posedge > for aa in xrange(4): > for bb in xrange(4): > a.next = aa > b.next = bb > yield clock.posedge > yield clock.posedge > assert cs == (a+b) > assert cc == (a+b) > raise StopSimulation > > Simulation((tb_clock,tb_dut_s,tb_dut_c,tb_stim)).run() > toVerilog(m_add_seq,clock,reset,a,b,cs) > toVerilog(m_add_comb,a,b,cc) > > > > > ------------------------------------------------------------------------------ > Own the Future-Intel(R) Level Up Game Demo Contest 2013 > Rise to greatness in Intel's independent game demo contest. Compete > for recognition, cash, and the chance to get your game on Steam. > $5K grand prize plus 10 genre and skill prizes. Submit your demo > by 6/6/13. http://altfarm.mediaplex.com/ad/ck/12124-176961-30367-2 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |
From: Christopher F. <chr...@gm...> - 2013-04-02 15:41:23
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On 4/2/2013 10:17 AM, Per Karlsson wrote: > There was an example in my original post. But of course there may be > something else that's wrong with that. > Especially since I just tried your example... and it works! :) > /Per > > Doh, missed the original example, will give it another look and see I see anything. .chris |
From: Christopher F. <chr...@gm...> - 2013-04-02 16:09:58
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On 4/2/2013 10:40 AM, Christopher Felton wrote: > On 4/2/2013 10:17 AM, Per Karlsson wrote: >> There was an example in my original post. But of course there may be >> something else that's wrong with that. >> Especially since I just tried your example... and it works! :) >> /Per >> >> > > Doh, missed the original example, will give it another > look and see I see anything. > > .chris > The difference between my example and the one you provided is that the function is in the local scope (in the original example). If I modify your example slightly it works in the /@always_comb/. I don't know if a local function working in the sequential just happens to work or if the local function not working in the comb is a bug. I will investigate (at some point :) ). Regards, Chris ~~~~ [modified example] ~~~~ from myhdl import * def f(a): out = intbv(0)[len(a):] if a<3: out[:] = a else: out[:] = 0 return out def w(a, b, c, clk): @always_comb def cm(): b.next = f(a) @always(clk.posedge) def ck(): c.next = f(a) return instances() def test(): a = Signal(intbv(0)[10:]) b = Signal(intbv(0)[10:]) c = Signal(intbv(0)[10:]) clk = Signal(bool(0)) dut = toVerilog(w, a, b,c ,clk) return instances() s = Simulation(test()) s.run() |