Thread: [myhdl-list] 0.8 Type mismatch in enum item comparison
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From: Jan C. <jan...@mu...> - 2012-05-31 13:10:48
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$ ./testSdp3o4.py
Traceback (most recent call last):
File "./testSdp3o4.py", line 41, in <module>
simulate(240)
File "./testSdp3o4.py", line 37, in simulate
tb = traceSignals(testSdp3o4)
File
"/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
89, in __call__
_writeVcdSigs(vcdfile, h.hierarchy)
File
"/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
146, in _writeVcdSigs
if s._val == None:
File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
117, in __eq__
raise TypeError("Type mismatch in enum item comparison")
TypeError: Type mismatch in enum item comparison
No problem with 0.7. Should I try to track it down?
Jan Coombs
--
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From: Christopher F. <chr...@gm...> - 2012-05-31 13:26:49
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On 5/31/2012 8:10 AM, Jan Coombs wrote:
> $ ./testSdp3o4.py
> Traceback (most recent call last):
> File "./testSdp3o4.py", line 41, in<module>
> simulate(240)
> File "./testSdp3o4.py", line 37, in simulate
> tb = traceSignals(testSdp3o4)
> File
> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
> 89, in __call__
> _writeVcdSigs(vcdfile, h.hierarchy)
> File
> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
> 146, in _writeVcdSigs
> if s._val == None:
> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
> 117, in __eq__
> raise TypeError("Type mismatch in enum item comparison")
> TypeError: Type mismatch in enum item comparison
>
> No problem with 0.7. Should I try to track it down?
>
> Jan Coombs
No might be important for you design! Jan D. added
some nice features to help debug the use of enums
(could be your case). Hopefully, 0.8 is flagging
(throwing an exception) for incorrect use of an e
num, where 0.7 will not.
You might want to try and run the test without
traceSignals and you may get more information.
Regards,
Chris
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From: Jan C. <jan...@mu...> - 2012-05-31 15:08:22
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On 31/05/12 14:26, Christopher Felton wrote:
> On 5/31/2012 8:10 AM, Jan Coombs wrote:
>> $ ./testSdp3o4.py
>> Traceback (most recent call last):
>> File "./testSdp3o4.py", line 41, in<module>
>> simulate(240)
>> File "./testSdp3o4.py", line 37, in simulate
>> tb = traceSignals(testSdp3o4)
>> File
>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>> 89, in __call__
>> _writeVcdSigs(vcdfile, h.hierarchy)
>> File
>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>> 146, in _writeVcdSigs
>> if s._val == None:
>> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
>> 117, in __eq__
>> raise TypeError("Type mismatch in enum item comparison")
>> TypeError: Type mismatch in enum item comparison
>>
>> No problem with 0.7. Should I try to track it down?
>>
>> Jan Coombs
>
> No might be important for you design! Jan D. added
> some nice features to help debug the use of enums
> (could be your case). Hopefully, 0.8 is flagging
> (throwing an exception) for incorrect use of an e
> num, where 0.7 will not.
>
> You might want to try and run the test without
> traceSignals and you may get more information.
It has taken me a long time to change the test code, but am now
running without and with traceSignals. Surprisingly I did not get
more information; without traceSignals there is no error.
So the error only appears with latest 0.8 when producing trace.
Jan Coombs.
--
###############
print;print"just sim"
sim = Simulation(testSdp3o4())
sim.run(240)
###############
def simulate(timesteps):
tb = traceSignals(testSdp3o4)
sim = Simulation(tb)
sim.run(timesteps)
print;print"sim & trace"
simulate(240)
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From: Christopher F. <chr...@gm...> - 2012-06-01 01:56:02
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On 5/31/12 10:07 AM, Jan Coombs wrote:
> On 31/05/12 14:26, Christopher Felton wrote:
>> On 5/31/2012 8:10 AM, Jan Coombs wrote:
>>> $ ./testSdp3o4.py
>>> Traceback (most recent call last):
>>> File "./testSdp3o4.py", line 41, in<module>
>>> simulate(240)
>>> File "./testSdp3o4.py", line 37, in simulate
>>> tb = traceSignals(testSdp3o4)
>>> File
>>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>>> 89, in __call__
>>> _writeVcdSigs(vcdfile, h.hierarchy)
>>> File
>>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>>> 146, in _writeVcdSigs
>>> if s._val == None:
>>> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
>>> 117, in __eq__
>>> raise TypeError("Type mismatch in enum item comparison")
>>> TypeError: Type mismatch in enum item comparison
>>>
>>> No problem with 0.7. Should I try to track it down?
>>>
>>> Jan Coombs
>>
>> No might be important for you design! Jan D. added
>> some nice features to help debug the use of enums
>> (could be your case). Hopefully, 0.8 is flagging
>> (throwing an exception) for incorrect use of an e
>> num, where 0.7 will not.
>>
>> You might want to try and run the test without
>> traceSignals and you may get more information.
>
> It has taken me a long time to change the test code, but am now
> running without and with traceSignals. Surprisingly I did not get
> more information; without traceSignals there is no error.
>
> So the error only appears with latest 0.8 when producing trace.
>
> Jan Coombs.
I sometimes like my testbenches to have three sim
modes selectable
if simType == 'trace':
dut = traceSignals(ModuleToTest, ...)
elif simType == 'cosim':
dut = CoSimulation(ModuleToTest, ...)
else
dut = ModuleToTest(..., )
Regards,
Chris
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From: Jan C. <jan...@mu...> - 2012-06-04 11:01:56
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On 01/06/12 02:55, Christopher Felton wrote:
. . .
>
> I sometimes like my testbenches to have three sim
> modes selectable
>
> if simType == 'trace':
> dut = traceSignals(ModuleToTest, ...)
> elif simType == 'cosim':
> dut = CoSimulation(ModuleToTest, ...)
> else
> dut = ModuleToTest(..., )
>
Thanks, looks neat, however, after a couple of hours I still
couldn't see how to integrate this with my cutrent test code.
I also have similar problems with some of the material on
myhdl.org. As expert to expert communication it is very good, but
often lacks enough repetitive or common code for me to be able to
spot the design patterns.
In order to use your code above I would either need to have a full
understanding of what is happening, which would allow me to work
out how to integrate this code fragment, or have you provide a full
test harness code sample which I could modify to suit myself.
Jan Coombs.
--
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From: Christopher F. <chr...@gm...> - 2012-06-04 11:14:54
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On 6/4/2012 6:01 AM, Jan Coombs wrote: > On 01/06/12 02:55, Christopher Felton wrote: > . . . >> >> I sometimes like my testbenches to have three sim >> modes selectable >> >> if simType == 'trace': >> dut = traceSignals(ModuleToTest, ...) >> elif simType == 'cosim': >> dut = CoSimulation(ModuleToTest, ...) >> else >> dut = ModuleToTest(..., ) >> > Thanks, looks neat, however, after a couple of hours I still > couldn't see how to integrate this with my cutrent test code. > > I also have similar problems with some of the material on > myhdl.org. As expert to expert communication it is very good, but > often lacks enough repetitive or common code for me to be able to > spot the design patterns. > > In order to use your code above I would either need to have a full > understanding of what is happening, which would allow me to work > out how to integrate this code fragment, or have you provide a full > test harness code sample which I could modify to suit myself. > > Jan Coombs. This might help as an example, select traceSignal vs. no traceSignal, http://www.myhdl.org/doku.php/users:cfelton:projects:recursivefft Regards, Chris |
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From: Jan D. <ja...@ja...> - 2012-05-31 14:55:46
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On 05/31/2012 03:10 PM, Jan Coombs wrote:
> $ ./testSdp3o4.py
> Traceback (most recent call last):
> File "./testSdp3o4.py", line 41, in<module>
> simulate(240)
> File "./testSdp3o4.py", line 37, in simulate
> tb = traceSignals(testSdp3o4)
> File
> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
> 89, in __call__
> _writeVcdSigs(vcdfile, h.hierarchy)
> File
> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
> 146, in _writeVcdSigs
> if s._val == None:
> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
> 117, in __eq__
> raise TypeError("Type mismatch in enum item comparison")
> TypeError: Type mismatch in enum item comparison
>
> No problem with 0.7. Should I try to track it down?
Mm, this is due to the more restrictive comparisons on EnumItemType.
Now, that 's._val == None' test is wrong also, the idiomatic test
is 'if s._val is None'. Could you check whether things work
when you make that change? (line 146 in _traceSignals.py).
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
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From: Jan C. <jan...@mu...> - 2012-05-31 15:14:22
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On 31/05/12 15:55, Jan Decaluwe wrote:
> On 05/31/2012 03:10 PM, Jan Coombs wrote:
>> $ ./testSdp3o4.py
>> Traceback (most recent call last):
>> File "./testSdp3o4.py", line 41, in<module>
>> simulate(240)
>> File "./testSdp3o4.py", line 37, in simulate
>> tb = traceSignals(testSdp3o4)
>> File
>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>> 89, in __call__
>> _writeVcdSigs(vcdfile, h.hierarchy)
>> File
>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>> 146, in _writeVcdSigs
>> if s._val == None:
>> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
>> 117, in __eq__
>> raise TypeError("Type mismatch in enum item comparison")
>> TypeError: Type mismatch in enum item comparison
>>
>> No problem with 0.7. Should I try to track it down?
>
> Mm, this is due to the more restrictive comparisons on EnumItemType.
>
> Now, that 's._val == None' test is wrong also, the idiomatic test
> is 'if s._val is None'. Could you check whether things work
> when you make that change? (line 146 in _traceSignals.py).
That fixed it, thanks.
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From: Jan D. <ja...@ja...> - 2012-05-31 20:20:14
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On 05/31/2012 05:13 PM, Jan Coombs wrote:
> On 31/05/12 15:55, Jan Decaluwe wrote:
>> On 05/31/2012 03:10 PM, Jan Coombs wrote:
>>> $ ./testSdp3o4.py
>>> Traceback (most recent call last):
>>> File "./testSdp3o4.py", line 41, in<module>
>>> simulate(240)
>>> File "./testSdp3o4.py", line 37, in simulate
>>> tb = traceSignals(testSdp3o4)
>>> File
>>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>>> 89, in __call__
>>> _writeVcdSigs(vcdfile, h.hierarchy)
>>> File
>>> "/home/jan/work/projects/MyHDL/myhdl/myhdl/_traceSignals.py", line
>>> 146, in _writeVcdSigs
>>> if s._val == None:
>>> File "/home/jan/work/projects/MyHDL/myhdl/myhdl/_enum.py", line
>>> 117, in __eq__
>>> raise TypeError("Type mismatch in enum item comparison")
>>> TypeError: Type mismatch in enum item comparison
>>>
>>> No problem with 0.7. Should I try to track it down?
>>
>> Mm, this is due to the more restrictive comparisons on EnumItemType.
>>
>> Now, that 's._val == None' test is wrong also, the idiomatic test
>> is 'if s._val is None'. Could you check whether things work
>> when you make that change? (line 146 in _traceSignals.py).
>
> That fixed it, thanks.
Ok, I have made this change in 0.8-dev.
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
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