myhdl-list

[myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi,

I am new to myHDL and it seems to be a powerful tool.
Today, I need some help to locate the reason of the below exception.
Because there are no clue to indicate the line of the issue, I am 
currently blocked in my evaluation of myHDL.

Thank you in advance.

Thoma

Traceback (most recent call last):
  File "bidir_serial.py", line 209, in <module>
    convert2verilog(bidir_serial)
  File "bidir_serial.py", line 200, in convert2verilog
    convert(toVerilog, architecture)
  File "bidir_serial.py", line 194, in convert
    converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py", 
line 142, in __call__
    genlist = _analyzeGens(arglist, h.absnames)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 174, in _analyzeGens
    v.visit(tree)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 1078, in visit_Module
    self.generic_visit(node)
  File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
    self.visit(item)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 1154, in visit_FunctionDef
    self.visit(n)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 744, in visit_If
    self.visitList(node.else_)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py", line 
161, in visitList
    self.visit(n)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 740, in visit_If
    self.visitList(suite)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py", line 
161, in visitList
    self.visit(n)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 770, in visit_If
    if (len(choices) == _getNritems(var1.obj)) or node.else_:
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py", 
line 407, in _getNritems
    raise TypeError("Unexpected type")
TypeError: Unexpected type

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Tom D. <td...@di...>]

Not sure but have you simulated it in MyHDL? Usually that will help 
expose problems better than trying to go directly to Verilog.

On 05/21/2012 03:54 PM, Thoma HAUC wrote:
> Hi,
>
> I am new to myHDL and it seems to be a powerful tool.
> Today, I need some help to locate the reason of the below exception.
> Because there are no clue to indicate the line of the issue, I am
> currently blocked in my evaluation of myHDL.
>
> Thank you in advance.
>
> Thoma
>
> Traceback (most recent call last):
>    File "bidir_serial.py", line 209, in<module>
>      convert2verilog(bidir_serial)
>    File "bidir_serial.py", line 200, in convert2verilog
>      convert(toVerilog, architecture)
>    File "bidir_serial.py", line 194, in convert
>      converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py",
> line 142, in __call__
>      genlist = _analyzeGens(arglist, h.absnames)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 174, in _analyzeGens
>      v.visit(tree)
>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>      return visitor(node)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 1078, in visit_Module
>      self.generic_visit(node)
>    File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>      self.visit(item)
>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>      return visitor(node)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 1154, in visit_FunctionDef
>      self.visit(n)
>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>      return visitor(node)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 744, in visit_If
>      self.visitList(node.else_)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py", line
> 161, in visitList
>      self.visit(n)
>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>      return visitor(node)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 740, in visit_If
>      self.visitList(suite)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py", line
> 161, in visitList
>      self.visit(n)
>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>      return visitor(node)
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 770, in visit_If
>      if (len(choices) == _getNritems(var1.obj)) or node.else_:
>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
> line 407, in _getNritems
>      raise TypeError("Unexpected type")
> TypeError: Unexpected type
>
>
> ------------------------------------------------------------------------------
> Live Security Virtual Conference
> Exclusive live event will cover all the ways today's security and
> threat landscape has changed and how IT managers can respond. Discussions
> will include endpoint security, mobile security and the latest in malware
> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Tom,

I already simulated the design without any issue.
The exception raises only during verilog generation process.

Thoma

> Not sure but have you simulated it in MyHDL? Usually that will help
> expose problems better than trying to go directly to Verilog.
> 
> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>> Hi,
>>
>> I am new to myHDL and it seems to be a powerful tool.
>> Today, I need some help to locate the reason of the below exception.
>> Because there are no clue to indicate the line of the issue, I am
>> currently blocked in my evaluation of myHDL.
>>
>> Thank you in advance.
>>
>> Thoma
>>
>> Traceback (most recent call last):
>>    File "bidir_serial.py", line 209, in<module>
>>      convert2verilog(bidir_serial)
>>    File "bidir_serial.py", line 200, in convert2verilog
>>      convert(toVerilog, architecture)
>>    File "bidir_serial.py", line 194, in convert
>>      converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py",
>> line 142, in __call__
>>      genlist = _analyzeGens(arglist, h.absnames)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 174, in _analyzeGens
>>      v.visit(tree)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 1078, in visit_Module
>>      self.generic_visit(node)
>>    File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>      self.visit(item)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 1154, in visit_FunctionDef
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 744, in visit_If
>>      self.visitList(node.else_)
>>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>    line
>> 161, in visitList
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 740, in visit_If
>>      self.visitList(suite)
>>    File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>    line
>> 161, in visitList
>>      self.visit(n)
>>    File "/usr/lib/python2.7/ast.py", line 241, in visit
>>      return visitor(node)
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 770, in visit_If
>>      if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>    File
>>    "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>> line 407, in _getNritems
>>      raise TypeError("Unexpected type")
>> TypeError: Unexpected type

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

Looks like there is an upfront error check missing,
could you post your code or a simplified version
that exposes the error?

On 05/24/2012 08:43 PM, Thoma HAUC wrote:
> Hi Tom,
>
> I already simulated the design without any issue.
> The exception raises only during verilog generation process.
>
> Thoma
>
>> Not sure but have you simulated it in MyHDL? Usually that will help
>> expose problems better than trying to go directly to Verilog.
>>
>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>> Hi,
>>>
>>> I am new to myHDL and it seems to be a powerful tool.
>>> Today, I need some help to locate the reason of the below exception.
>>> Because there are no clue to indicate the line of the issue, I am
>>> currently blocked in my evaluation of myHDL.
>>>
>>> Thank you in advance.
>>>
>>> Thoma
>>>
>>> Traceback (most recent call last):
>>>     File "bidir_serial.py", line 209, in<module>
>>>       convert2verilog(bidir_serial)
>>>     File "bidir_serial.py", line 200, in convert2verilog
>>>       convert(toVerilog, architecture)
>>>     File "bidir_serial.py", line 194, in convert
>>>       converter(architecture, clr, clk, run, ld, datain, rdy, serialout)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVerilog.py",
>>> line 142, in __call__
>>>       genlist = _analyzeGens(arglist, h.absnames)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 174, in _analyzeGens
>>>       v.visit(tree)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 1078, in visit_Module
>>>       self.generic_visit(node)
>>>     File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>>       self.visit(item)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 1154, in visit_FunctionDef
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 744, in visit_If
>>>       self.visitList(node.else_)
>>>     File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>     line
>>> 161, in visitList
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 740, in visit_If
>>>       self.visitList(suite)
>>>     File "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>     line
>>> 161, in visitList
>>>       self.visit(n)
>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>       return visitor(node)
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 770, in visit_If
>>>       if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>>     File
>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>> line 407, in _getNritems
>>>       raise TypeError("Unexpected type")
>>> TypeError: Unexpected type
>
>
> ------------------------------------------------------------------------------
> Live Security Virtual Conference
> Exclusive live event will cover all the ways today's security and
> threat landscape has changed and how IT managers can respond. Discussions
> will include endpoint security, mobile security and the latest in malware
> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Thoma H. <tho...@gm...>]

Hi Jan,

Are you able to print out the line number that raises the exception?
Could you explain me what I did wrong?

In advance many thanks

Here is the python source:

LOW, HIGH = bool(0), bool(1)
INACTIVE, ACTIVE = LOW, HIGH
StateEnum = enum('IDLE', 'HSYNC', 'SYNC', 'SYNC2', 'HADDR', 'ADDR', 
'ADDR2', 'ADDR3', 'HSEND', 'SEND', 'SEND2', 'SEND3', 'HRECV', 'RECV', 
'HRECV2', 'RECV2')

def bidir_serial_master(clr, clk, run, ack, serialin, datain, rdy, oe, 
serialout, dataout):

    state = Signal(StateEnum.IDLE)
    timeout = Signal(INACTIVE)
    count = Signal(intbv(0)[3:])
    inputreg = Signal(intbv(0)[8:])
    internaldata = Signal(intbv(0)[8:])
    int_rdy = Signal(INACTIVE)
    int_serialout = Signal(HIGH)

    @always_comb
    def copy():
        rdy.next = int_rdy
        serialout.next = int_serialout

    @always_comb
    def outputenable():
        if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC) or 
(state == StateEnum.SYNC2) or (state == StateEnum.HADDR) or (state == 
StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.HSEND) or (state == 
StateEnum.SEND) or (state == StateEnum.SEND2) or (state == 
StateEnum.SEND3)):
            oe.next = ACTIVE
        else:
            oe.next = INACTIVE

    @always_comb
    def ready():
        if ((state == StateEnum.IDLE) or (state == StateEnum.SYNC) or 
(state == StateEnum.ADDR) or (state == StateEnum.RECV2)):
            int_rdy.next = ACTIVE
        elif (state == StateEnum.SEND):
            int_rdy.next = run
        else:
            int_rdy.next = INACTIVE

    @always_comb
    def send_data():
        if ((state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or 
(state == StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3)):
            int_serialout.next = internaldata[count]
        elif ((state == StateEnum.HADDR) or (state == StateEnum.HSEND) or 
(state == StateEnum.HRECV)):
            int_serialout.next = LOW
        else:
            int_serialout.next = HIGH

    @always(clk.posedge, clr.posedge)
    def storage():
        if (clr == ACTIVE):
            inputreg.next = 0
            internaldata.next = 0
        else:
            if ((ack == ACTIVE) and (int_rdy == ACTIVE)):
                inputreg.next = datain
            elif ((count == 7) and ((state == StateEnum.SYNC2) or (state 
== StateEnum.ADDR3) or (state == StateEnum.SEND2))):
                internaldata.next = inputreg
            if ((state == StateEnum.RECV) or (state == StateEnum.RECV2)):
                if (count == 7):
                    dataout.next[7:] = internaldata[7:]
                    dataout.next[7] = serialin
                else:
                    internaldata.next[count] = serialin

    @always(clk.posedge, clr.posedge)
    def counter():
        if (clr == ACTIVE):
            count.next = 0
            timeout.next = INACTIVE
        else:
            if ((state == StateEnum.SYNC) or (state == StateEnum.SYNC2) 
or (state == StateEnum.ADDR) or (state == StateEnum.ADDR2) or (state == 
StateEnum.ADDR3) or (state == StateEnum.SEND) or (state == 
StateEnum.SEND2) or (state == StateEnum.SEND3) or (state == 
StateEnum.RECV) or (state == StateEnum.RECV2)):
                count.next = (count + 1) % 8
            if (count == 6):
                timeout.next = ACTIVE
            if (count == 7):
                timeout.next = INACTIVE

    @always(clk.posedge, clr.posedge)
    def fsm():
        if (clr == ACTIVE):
            state.next = StateEnum.IDLE
        else:
            if (state == StateEnum.IDLE):
                if (run == ACTIVE):
                    state.next = StateEnum.SYNC
            elif (state == StateEnum.SYNC):
                if (ack == ACTIVE):
                    state.next = StateEnum.HSYNC
            elif (state == StateEnum.HSYNC):
                state.next = StateEnum.SYNC2
            elif (state == StateEnum.SYNC2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HADDR
            elif (state == StateEnum.HADDR):
                state.next = StateEnum.ADDR
            elif (state == StateEnum.ADDR):
                if (internaldata[0] == LOW):
                    state.next = StateEnum.ADDR2
                elif (ack == ACTIVE):
                    state.next = StateEnum.ADDR3
            elif (state == StateEnum.ADDR2):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HRECV
            elif (state == StateEnum.ADDR3):
                if (timeout == ACTIVE):
                        state.next = StateEnum.HSEND
            elif (state == StateEnum.HSEND):
                state.next = StateEnum.SEND
            elif (state == StateEnum.SEND):
                if (run == INACTIVE):
                    state.next = StateEnum.SEND3
                elif (ack == ACTIVE):
                    state.next = StateEnum.SEND2
            elif (state == StateEnum.SEND2):
                if (timeout == ACTIVE):
                    state.next = StateEnum.HSEND
            elif (state == StateEnum.SEND3):
                if (timeout == ACTIVE):
                    state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV):
                state.next = StateEnum.RECV
            elif (state == StateEnum.RECV):
                if (timeout == ACTIVE):
                    if (run == ACTIVE):
                        state.next = StateEnum.HRECV2
                    else:
                        state.next = StateEnum.IDLE
            elif (state == StateEnum.HRECV2):
                state.next = StateEnum.RECV2
            elif (state == StateEnum.RECV2):
                if (ack == ACTIVE):
                    state.next = StateEnum.RECV
            else:
                state.next = StateEnum.IDLE

    return instances()

Thoma

> Looks like there is an upfront error check missing,
> could you post your code or a simplified version that exposes the error?
> 
> On 05/24/2012 08:43 PM, Thoma HAUC wrote:
>> Hi Tom,
>>
>> I already simulated the design without any issue.
>> The exception raises only during verilog generation process.
>>
>> Thoma
>>
>>> Not sure but have you simulated it in MyHDL? Usually that will help
>>> expose problems better than trying to go directly to Verilog.
>>>
>>> On 05/21/2012 03:54 PM, Thoma HAUC wrote:
>>>> Hi,
>>>>
>>>> I am new to myHDL and it seems to be a powerful tool.
>>>> Today, I need some help to locate the reason of the below exception.
>>>> Because there are no clue to indicate the line of the issue, I am
>>>> currently blocked in my evaluation of myHDL.
>>>>
>>>> Thank you in advance.
>>>>
>>>> Thoma
>>>>
>>>> Traceback (most recent call last):
>>>>     File "bidir_serial.py", line 209, in<module>
>>>>       convert2verilog(bidir_serial)
>>>>     File "bidir_serial.py", line 200, in convert2verilog
>>>>       convert(toVerilog, architecture)
>>>>     File "bidir_serial.py", line 194, in convert
>>>>       converter(architecture, clr, clk, run, ld, datain, rdy,
>>>>       serialout)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/
_toVerilog.py",
>>>> line 142, in __call__
>>>>       genlist = _analyzeGens(arglist, h.absnames)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 174, in _analyzeGens
>>>>       v.visit(tree)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 1078, in visit_Module
>>>>       self.generic_visit(node)
>>>>     File "/usr/lib/python2.7/ast.py", line 249, in generic_visit
>>>>       self.visit(item)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 1154, in visit_FunctionDef
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 744, in visit_If
>>>>       self.visitList(node.else_)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>>     line
>>>> 161, in visitList
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 740, in visit_If
>>>>       self.visitList(suite)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_misc.py",
>>>>     line
>>>> 161, in visitList
>>>>       self.visit(n)
>>>>     File "/usr/lib/python2.7/ast.py", line 241, in visit
>>>>       return visitor(node)
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 770, in visit_If
>>>>       if (len(choices) == _getNritems(var1.obj)) or node.else_:
>>>>     File
>>>>     "/usr/lib/python2.7/site-packages/myhdl/conversion/_analyze.py",
>>>> line 407, in _getNritems
>>>>       raise TypeError("Unexpected type")
>>>> TypeError: Unexpected type
>>
>>
>> 
------------------------------------------------------------------------------
>> Live Security Virtual Conference Exclusive live event will cover all
>> the ways today's security and threat landscape has changed and how IT
>> managers can respond. Discussions will include endpoint security,
>> mobile security and the latest in malware threats.
>> http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>      @always_comb
>      def outputenable():
>          if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)

I believe this is the issue.  There was a recent thread on this.  It 
looks like enums fail in an always_comb.  A simple test case was 
submitted recently.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/24/2012 10:53 PM, Christopher Felton wrote:
> On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>>       @always_comb
>>       def outputenable():
>>           if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)
>
> I believe this is the issue.  There was a recent thread on this.  It
> looks like enums fail in an always_comb.  A simple test case was
> submitted recently.

No, it was something else. Can you point me to the
post/author of the other problem(s). I lost track a little
but I will look into it with priority.

Also, I propose to start using the bug tracker again, for
formal bug reporting (after discussing it here preferably).
Note that you can attach files to bug reports. I have
done this for the bug that was just reported.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 6:09 AM, Jan Decaluwe wrote:
> On 05/24/2012 10:53 PM, Christopher Felton wrote:
>> On 5/24/2012 3:23 PM, Thoma HAUC wrote:
>>>        @always_comb
>>>        def outputenable():
>>>            if ((state == StateEnum.HSYNC) or (state == StateEnum.SYNC)
>>
>> I believe this is the issue.  There was a recent thread on this.  It
>> looks like enums fail in an always_comb.  A simple test case was
>> submitted recently.
>
> No, it was something else. Can you point me to the
> post/author of the other problem(s). I lost track a little
> but I will look into it with priority.
>
> Also, I propose to start using the bug tracker again, for
> formal bug reporting (after discussing it here preferably).
> Note that you can attach files to bug reports. I have
> done this for the bug that was just reported.
>

There have been a couple possible bugs reported.  It was my intent to 
submit patches with tests that exposed the issues.  Ah, such dreaming, 
time to work on fun things :)

Here is a snip from the a previous thread, using the enum in a 
always_comb didn't appear to work.  I tested quickly there could be a 
mistake on my part.

> I think your issue with using the enum() is in combination with the
> always_comb decorator.  The enums don't seem to work in an always_comb?
>   I didn't realize this limitation existed.  The following is the simple
> example I used (one of your previous questions) to see if this was true
> or not.
>
>      from myhdl import *
>
>      def case_ex1(clk, key, led):
>          tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>          @always(clk.posedge)
>          def hdl():
>              if   key==tKey.UP:    led.next = 0xDE
>              elif key==tKey.DOWN:  led.next = 0xCA
>              elif key==tKey.LEFT:  led.next = 0xFB
>              elif key==tKey.RIGHT: led.next = 0xAD
>              else:                 led.next = 0x00
>
>          return hdl
>
>      def case_ex2(key, led):
>          tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>          @always_comb
>          def hdl():
>              if   key==tKey.UP:    led.next = 0xDE
>              elif key==tKey.DOWN:  led.next = 0xCA
>              elif key==tKey.LEFT:  led.next = 0xFB
>              elif key==tKey.RIGHT: led.next = 0xAD
>              else:                 led.next = 0x00
>
>          return hdl
>
> In the above, the second does not convert correctly and fails the
> freevar check in the _analyzeGens, determines the enum is an unsupported
> type.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/25/2012 02:54 PM, Christopher Felton wrote:

>
>> I think your issue with using the enum() is in combination with the
>> always_comb decorator.  The enums don't seem to work in an always_comb?
>>    I didn't realize this limitation existed.  The following is the simple
>> example I used (one of your previous questions) to see if this was true
>> or not.
>>
>>       from myhdl import *
>>
>>       def case_ex1(clk, key, led):
>>           tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>>           @always(clk.posedge)
>>           def hdl():
>>               if   key==tKey.UP:    led.next = 0xDE
>>               elif key==tKey.DOWN:  led.next = 0xCA
>>               elif key==tKey.LEFT:  led.next = 0xFB
>>               elif key==tKey.RIGHT: led.next = 0xAD
>>               else:                 led.next = 0x00
>>
>>           return hdl
>>
>>       def case_ex2(key, led):
>>           tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
>>           @always_comb
>>           def hdl():
>>               if   key==tKey.UP:    led.next = 0xDE
>>               elif key==tKey.DOWN:  led.next = 0xCA
>>               elif key==tKey.LEFT:  led.next = 0xFB
>>               elif key==tKey.RIGHT: led.next = 0xAD
>>               else:                 led.next = 0x00
>>
>>           return hdl
>>
>> In the above, the second does not convert correctly and fails the
>> freevar check in the _analyzeGens, determines the enum is an unsupported
>> type.

How can key be defined, if the enum is defined inside the module?

Can you or Jan C provide me with a short but complete example
(including signal defs and conversion call) that fails?
I'll start thinking after that :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
> On 05/25/2012 02:54 PM, Christopher Felton wrote:
<snip>

>
> How can key be defined, if the enum is defined inside the module?

Good question, in the original example the enum was being used as 
"constant" values.  And "key" was of type intbv.  The quick answer might 
have been don't mix types?

The odd thing I ran into is that it worked in the /always/ generator and 
not the /always_comb/.  Below is the complete example, you should be 
able to run it.

>
> Can you or Jan C provide me with a short but complete example
> (including signal defs and conversion call) that fails?
> I'll start thinking after that :-)
>

import myhdl
print myhdl.__version__
from myhdl import *

def case_ex1(clk, key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always(clk.posedge)
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

def case_ex2(key, led):
     tKey = enum('UP', 'DOWN', 'LEFT', 'RIGHT')
     @always_comb
     def hdl():
         if   key==tKey.UP:    led.next = 0xDE
         elif key==tKey.DOWN:  led.next = 0xCA
         elif key==tKey.LEFT:  led.next = 0xFB
         elif key==tKey.RIGHT: led.next = 0xAD
         else:                 led.next = 0x00

     return hdl

if __name__ == '__main__':
     clk = Signal(False)
     key = Signal(intbv(1, min=1, max=9))
     led = Signal(intbv(0)[8:])
     dip = Signal(intbv(0)[8:])

     print('Covert case_ex1')
     toVerilog(case_ex1, clk, key, led)
     toVHDL(case_ex1, clk, key, led)

     print('Convert case_ex2')
     toVerilog(case_ex2, key, led)
     toVHDL(case_ex2, key, led)


----------------
Output from run
----------------
   >> python case.py
   0.8dev
   Covert case_ex1
   Convert case_ex2
   Traceback (most recent call last):
     File "case.py", line 41, in <module>
       toVerilog(case_ex2, key, led)
_analyze.py", line 165, in _analyzeGens
     raise ConversionError(_error.UnsupportedType, n, info)
myhdl.ConversionError: File case.py, line 19: Object type is not 
supported in this context: tKey


Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/25/2012 4:22 PM, Christopher Felton wrote:
> On 5/25/2012 3:58 PM, Jan Decaluwe wrote:
>> On 05/25/2012 02:54 PM, Christopher Felton wrote:
> <snip>
>
>>
>> How can key be defined, if the enum is defined inside the module?
>
> Good question, in the original example the enum was being used as
> "constant" values.  And "key" was of type intbv.  The quick answer might
> have been don't mix types?
>
> The odd thing I ran into is that it worked in the /always/ generator and
> not the /always_comb/.  Below is the complete example, you should be
> able to run it.
>
>>
>> Can you or Jan C provide me with a short but complete example
>> (including signal defs and conversion call) that fails?
>> I'll start thinking after that :-)
>>
>

This example for the most part is probably *bunk*.  I thought I had 
extracted a portion of a larger example, which I might have.  But the 
strange thing here isn't that the /always_comb/ didn't convert it is 
that the /always/ *did* convert.  I got the cause and effect backwards.

I would (should) have noticed this if I had created a test.

def test():
     clk = Signal(False)
     key = Signal(intbv(1, min=1, max=9))
     led = Signal(intbv(0)[8:])
     dip = Signal(intbv(0)[8:])

     @always(delay(2))
     def tb_clkgen():
         clk.next = not clk

     @instance
     def tb_stimulus():
         for ii in range(1,key.max):
             yield clk.posedge
             print("key %d led %d" % (key, led))
             key.next = ii
         raise StopSimulation

     Simulation((tb_clkgen, tb_stimulus)).run()

-------------
Output
-------------
key 1 led 0
key 1 led 0
key 2 led 0
key 3 led 0
key 4 led 0
key 5 led 0
key 6 led 0
key 7 led 0

-------------

Again, the odd behavior is with the /always/ generator conversion.  I 
believe, it created valid logic.  The converted code should simulate 
correctly while the MyHDL code doesn't.

This is *not* the error that I reported earlier, that the enum cannot be 
used in an /always_comb/.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 25/05/12 23:19, Christopher Felton wrote:
[snip]
> This is *not* the error that I reported earlier, that the enum cannot be
> used in an /always_comb/.

I had hoped that the short tests I posted earlier would shed some 
light on this, but they only seem to demonstrate irregular case 
conversion.

The /always_comb/ problem still shows in my processor code when 
using enums, but converts ok when constants are used:

   if usingEnums:
     ExST = enum('Fetch1','Fetch2','NewAddr','Skip',  \
                     'Gap','Broken', encoding='one_hot')
     execState, execNextState =   \
                 [Signal(ExST.Fetch1) for i in range(2)]
   else:
     ExstFetch1,ExstFetch2,ExstNewAddr,ExstSkip,  \
                           ExstGap,ExstBroken = range(6)
     execState, execNextState =   \
                [Signal(intbv(0)[4:]) for i in range(2)]

The rest of the enum/const switch presently needs manual editing, 
but in summary, by process of elimination I have found that:

Assigning an enum to execNextState in an always_comb block produces 
the error:
   Object type is not supported in this context: ExST

In the clocked block which latches the next state, and in three 
other blocks where the state variable is compared with a constant, 
(ExST.xxx) this error is reported:
   TypeError: int() argument must be a string or a number, not 
'EnumItem'

Perhaps if I knew a little more of class notation I could have 
simple constants expressed in the same notation as enums, and 
simplify comparative testing.

Jan Coombs
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 26/05/12 00:28, Jan Coombs wrote:
> The /always_comb/ problem still shows in my processor code when
> using enums, but converts ok when constants are used:

The attached code shows a problem with using enum for state control 
inside an @always_comb process.  I have carefully cut this down 
from my working code to show just my conversion problem.

> Perhaps if I knew a little more of class notation I could have
> simple constants expressed in the same notation as enums, and
> simplify comparative testing.
I had a go at this, and it seems to produce the same errors as 
using enums.

Jan Coombs.
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/26/2012 10:49 AM, Jan Coombs wrote:
> On 26/05/12 00:28, Jan Coombs wrote:
>> The /always_comb/ problem still shows in my processor code when
>> using enums, but converts ok when constants are used:
>
> The attached code shows a problem with using enum for state control
> inside an @always_comb process. I have carefully cut this down from
> my working code to show just my conversion problem.

I would be really surprized if this is your original
problem, because it is related to enum signals which
are not driven, unlikely to be useful in a real design.

Anyway, I have "solved" the problem reported in development
by raising error messages on the use of undriven enum signals.
Supporting this would be easy in Verilog, but not in VHDL,
at least not at the top-level, where enums create some
complications.

Do you really have a need for undriven enum signals?


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 29/05/12 08:45, Jan Decaluwe wrote:

> Do you really have a need for undriven enum signals?

The code was only for conversion testing, by changing the 
commenting on the return lines.  Perhaps I should have left it in 
error display mode?:)

I could expand the code in order to show simulation as well as 
conversion, but wanted to save us both time.

As far as I could see the enum error returned by this snippet is 
the same as that from building my project, and using enums for the 
state constants.

Jan Coombs

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/29/2012 05:34 PM, Jan Coombs wrote:
> On 29/05/12 08:45, Jan Decaluwe wrote:
>
>> Do you really have a need for undriven enum signals?
>
> The code was only for conversion testing, by changing the
> commenting on the return lines.  Perhaps I should have left it in
> error display mode?:)
>
> I could expand the code in order to show simulation as well as
> conversion, but wanted to save us both time.
>
> As far as I could see the enum error returned by this snippet is
> the same as that from building my project, and using enums for the
> state constants.

Then I suggest to use the development version (either the default
branch, which is the maintenance branch for 0.7, or 0.8-dev)
to see if anything changed or becomes clearer.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 29/05/12 16:48, Jan Decaluwe wrote:
    . . .
> Then I suggest to use the development version (either the default
> branch, which is the maintenance branch for 0.7, or 0.8-dev)
> to see if anything changed or becomes clearer.

Have just updated 0.8 and error is the same:

raise ToVerilogError("Unexpected type for constant signal", s._name)
myhdl.ToVerilogError: Unexpected type for constant signal: execState_E

Jan Coombs
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 29/05/12 20:53, Jan Decaluwe wrote:
    . . .
> This is the hopefully clearer error message I just created
> in both branches.
Thanks, I like MyHDL like a long-lost friend, and hope to make much 
more progress together.

Attached is simplified the test code, as there still seems to be a 
problem.

Jan Coombs.
--

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 05:28, Christopher Felton wrote:
    ...
> I modified your code so that it does not have the "undriven enum
> Signals". Once you remove the undriven enum Signals this example
> converts without throwing and error.

I enthusiastically reverted the project code to use enums, but the 
error pattern there is still the same:

In the async process which assigns an enum to the execNextState 
signal I get:
   Object type is not supported in this context: ExST

In all other processes in which execNextState or execState are 
referenced I get:
   Unexpected type for constant signal: execState
which probably relates exclusively to referencing enum constants.


What bothers me is that you fixed my code by adding a process which 
appears to have no relation to the enum errors reported.

I further refined this conclusion by making your code asynchronous, 
and only enabling the statements which are needed to avoid 
unassigned signals.  Your fix still converts, although, when 
testing enums, the only difference is that the code does not return 
an unassigned intbv.

Your fix further disturbs me, because the only effective debug 
process for conversion errors I have found is to disable 
simulation, and selectively remove offending code refs from the 
return statements.  This is the opposite of your fix, which adds 
apparently unrelated code.

If your corrected code represents a valid response, then all of my 
debug efforts may be invalid.

In the attached code I have eliminated the problems you corrected, 
and the sample now demonstrates failure to convert in code using 
enums, while matching code using simple constants is ok.

The sandboxed code is now closer to my project, but let me know if 
you want to see the the project - about 13.5kB at present.

Back to you(s), and back to real work now.

Jan Coombs.
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/30/2012 01:20 AM, Jan Coombs wrote:
> On 29/05/12 20:53, Jan Decaluwe wrote:
> . . .
>> This is the hopefully clearer error message I just created
>> in both branches.
> Thanks, I like MyHDL like a long-lost friend, and hope to make much more progress together.
>
> Attached is simplified the test code, as there still seems to be a problem.

Same problem: a undriven enum signal, not supported currently.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 16:04, Jan Decaluwe wrote:
> On 05/30/2012 01:20 AM, Jan Coombs wrote:
>> On 29/05/12 20:53, Jan Decaluwe wrote:
>> . . .
>>> This is the hopefully clearer error message I just created
>>> in both branches.
>> Thanks, I like MyHDL like a long-lost friend, and hope to make much more progress together.
>>
>> Attached is simplified the test code, as there still seems to be a problem.
>
> Same problem: a undriven enum signal, not supported currently.
>
Wat zeg ye?  Looks like double-dutch to me:)

Groenten uit engeland, Jan.

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/30/2012 11:44 AM, Jan Coombs wrote:
> On 30/05/12 05:28, Christopher Felton wrote:
> ...
>> I modified your code so that it does not have the "undriven enum
>> Signals". Once you remove the undriven enum Signals this example
>> converts without throwing and error.
>
> I enthusiastically reverted the project code to use enums, but the error pattern there is still the same:
>
> In the async process which assigns an enum to the execNextState signal I get:
> Object type is not supported in this context: ExST

This is an error I had not seen so far from a failing test.

Cause: a too restrictive test on permitted free var types
in always_comb blocks. I have solved this in development.

Workaround: put enum definitions in the outer scope (outside the def)

Or use the development version, either branch.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan C. <jan...@mu...>]

On 30/05/12 17:16, Jan Decaluwe wrote:
    . . .
> This is an error I had not seen so far from a failing test.
>
> Cause: a too restrictive test on permitted free var types
> in always_comb blocks. I have solved this in development.

Excellent, thanks, project sims & converts now.

Next I need to finish making sure that my memory model matches the 
Actel Igloo nano on chip block RAM, and find the simplest way to 
convert using a target macro.

Kind regards, Jan Coombs.
-- 

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Jan D. <ja...@ja...>]

On 05/29/2012 06:34 PM, Jan Coombs wrote:
> On 29/05/12 16:48, Jan Decaluwe wrote:
>      . . .
>> Then I suggest to use the development version (either the default
>> branch, which is the maintenance branch for 0.7, or 0.8-dev)
>> to see if anything changed or becomes clearer.
>
> Have just updated 0.8 and error is the same:
>
> raise ToVerilogError("Unexpected type for constant signal", s._name)
> myhdl.ToVerilogError: Unexpected type for constant signal: execState_E

This is the hopefully clearer error message I just created
in both branches.

For intbv or bool, supporting undriven signals is simple,
by assigning the constant initial value. There may be a
use for this, e.g driving some signals on an external
interface to a constant value if some features are not used.

But for enums it creates some complications in VHDL, and
I don't see how this could be useful. I expect that your
completed design will not have them.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: Unexpected type with toVerilog

[Christopher F. <chr...@gm...>]

On 5/29/12 6:20 PM, Jan Coombs wrote:
> On 29/05/12 20:53, Jan Decaluwe wrote:
> . . .
>> This is the hopefully clearer error message I just created
>> in both branches.
> Thanks, I like MyHDL like a long-lost friend, and hope to make much more
> progress together.
>
> Attached is simplified the test code, as there still seems to be a problem.
>
> Jan Coombs.
> --
>

Jan C.

I modified your code so that it does not have the "undriven enum 
Signals".  Once you remove the undriven enum Signals this example 
converts without throwing and error.

Regards,
Chris