myhdl-list

[myhdl-list] conversion to case statement - odd behaviour?

[Jan C. <jan...@mu...>]

In this code the first condition is separated into a separate 'if' 
with the 'elif' lines becoming part of a verilog case statement:

   @always(keyDBclk.posedge)
   def ledLatchLogic():
     ''' connect push button event to action '''
     if   keyEventPB_SW==1:  ledLatch.next = ledLatch>>1
     elif keyEventPB_SW==2:  ledLatch.next = ~ledLatch
     elif keyEventPB_SW==4:  ledLatch.next = ~DIP_SW
     elif keyEventPB_SW==8:  ledLatch.next = (ledLatch<<1) & 255
     else:                   ledLatch.next = ledLatch

I have tried reversing the order of bit selection, and without the 
'else'/'default' clause.

Jan Coombs

Re: [myhdl-list] conversion to case statement - odd behaviour?

[Christopher F. <chr...@gm...>]

On 4/30/12 6:12 AM, Jan Coombs wrote:
> In this code the first condition is separated into a separate 'if'
> with the 'elif' lines becoming part of a verilog case statement:
>
>     @always(keyDBclk.posedge)
>     def ledLatchLogic():
>       ''' connect push button event to action '''
>       if   keyEventPB_SW==1:  ledLatch.next = ledLatch>>1
>       elif keyEventPB_SW==2:  ledLatch.next = ~ledLatch
>       elif keyEventPB_SW==4:  ledLatch.next = ~DIP_SW
>       elif keyEventPB_SW==8:  ledLatch.next = (ledLatch<<1)&  255
>       else:                   ledLatch.next = ledLatch
>
> I have tried reversing the order of bit selection, and without the
> 'else'/'default' clause.
>
> Jan Coombs
>
>

I reproduced your post and have encapsulated in a small example (can 
provide if needed).  But what I don't know is if this is bad or not.  Or 
if it is unintended conversion behavior.  It the converted code with the 
mix of if-else and case should synthesize fine (functionally equivalent) 
but I don't know if it is optimal for synthesis or not.

Regards,
Chris

Re: [myhdl-list] conversion to case statement - odd behaviour?

[Jan C. <jan...@mu...>]

On 10/05/12 03:14, Christopher Felton wrote:
>
> I reproduced your post and have encapsulated in a small example (can
> provide if needed).  But what I don't know is if this is bad or not.  Or
> if it is unintended conversion behavior.  It the converted code with the
> mix of if-else and case should synthesize fine (functionally equivalent)
> but I don't know if it is optimal for synthesis or not.

Thanks Chris, all help much appreciated. I was not concerned as 
this initially only seemed cosmetic, however, I have tried some 
further permutations, using enum, and separating the result latch. 
  Attached is the source and resulting Verilog files for each 
combination.  The one that interests me most will not convert:

jan@T60:~/work/projects/MyHDL/igloo-tests/SnL_58_LshiftLoadInvertRshift$ 
./test_SnL_58.py
<class 'myhdl._SuspendSimulation'>: Simulated 15000 timesteps
Traceback (most recent call last):
   File "./test_SnL_58.py", line 62, in <module>
     toVerilog(SnL_58, LEDs,PB_SW,DIP_SW, clk_20MHz,10000)
   File 
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVerilog.py", 
line 142, in __call__
     genlist = _analyzeGens(arglist, h.absnames)
   File 
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_analyze.py", 
line 165, in _analyzeGens
     _isMem(obj) or _isTupleOfInts(obj)
AssertionError
jan@T60:~/work/projects/MyHDL/igloo-tests/SnL_58_LshiftLoadInvertRshift$ 


I also have this problem in my main project, so getting a small 
example was a lucky catch.

Jan Coombs