myhdl-list

[myhdl-list] Signal has multiple drivers

[garyr <ga...@fi...>]

Code that appears to be OK when simulated produces errors "Signal has
multiple drivers" when I attempt to convert it to Verilog. In my case the
two drivers never access the signal at the same time so there should be no
problem. Google didn't turn up any useful information.

In one case a rather simple change eliminated the problem. Another
occurrence I eliminated by adding a multiplexer that routed a start and an
8-bit command signal to the shared module. A third occurrence involves an
unsigned division module having 32-bit parameters dividend, divisor and
quotient. The dividend and divisor signals would have multiple drivers.
Using a multiplexer approach here would be very costly in terms of bits. Is
there some other way of dealing with this problem? Couldn't MyHDL just issue
a warning?

[myhdl-list] Signal has multiple drivers

[Edward V. <dev...@sb...>]

Hello all,
Fairly new to vhdl.  Using a structural model with 8 instances.  Everything was working okay.
Started getting a message the Signal has multiple drivers.
Found a posting http://comments.gmane.org/gmane.comp.python.myhdl/1999
from Chris Felton to use a mux.

I see in the package generated with toVHDL
signal instance_7_addr_r: unsigned(5 downto 0); which is used by JPEG_TOP_INSTANCE_1_SDRAM_RD and
JPEG_TOP_INSTANCE_7_FILE_RD.

What I do not see in the package is the code for the muxLogic.

    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic    
which was part of JPEG_TOP_INSTANCE_7_FILE_RD.

def read_file_sdram(clk_fast, rst, eog, we_sdram, rst_file_in, addr_r1, addr_r2, sel ):
    addr_r = Signal(intbv(0)[6:])
    @always(clk_fast.negedge)
    def file_rd():
        if (rst_file_in == 0):
            rst.next = 1
            addr_r.next = 0
            we_sdram.next = 1
        else:
            if (rst == 1):
                rst.next = 0
            elif (eog == 0):
                if (addr_r <= 48):
                    
                    addr_r.next = addr_r + 1
            else:
                we_sdram.next = 0
    return file_rd
    @always_comb
    def muxLogic():
        addr_r.next = addr_r1
        if sel == 1:
            addr_r.next = addr_r2
    return muxLogic

I am trying to run a simulation using ISE 14.7 at the moment.
I know I need to use addr_r1, addr_r2, and sel for JPEG_TOP_INSTANCE_7_FILE_RD. Which is where is where
I defined the muxLogic.  JPEG_TOP_INSTANCE_7_FILE_RD and JPEG_TOP_INSTANCE_1_SDRAM_RD
both will be used in simulation.  Only JPEG_TOP_INSTANCE_1_SDRAM_RD & JPEG_TOP_INSTANCE_4_FSM will be used
in the bit file.  This uses addr_r which is not part of entity jpeg_top.
Did I put the muxLogic code in the wrong place?
Thanks in advance for any and all help.


 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Signal has multiple drivers

[Josy B. <jos...@gm...>]

The read_file_sdram definition has two return statements. The first one 
will be executed, shutting out the rest of the code. You have to make a 
single 'lumped' return after the last process, e.g. <return file_rd, 
muxLogic>
You will then get the VHDL-warning that addr_r has multiple drivers 
because you specify an <addr_r.next = ...> operation in both processes.

Re: [myhdl-list] Signal has multiple drivers

[Christopher F. <chr...@gm...>]

On 11/22/11 6:29 PM, garyr wrote:
> Code that appears to be OK when simulated produces errors "Signal has
> multiple drivers" when I attempt to convert it to Verilog. In my case the
> two drivers never access the signal at the same time so there should be no
> problem. Google didn't turn up any useful information.
>
> In one case a rather simple change eliminated the problem. Another
> occurrence I eliminated by adding a multiplexer that routed a start and an
> 8-bit command signal to the shared module. A third occurrence involves an
> unsigned division module having 32-bit parameters dividend, divisor and
> quotient. The dividend and divisor signals would have multiple drivers.
> Using a multiplexer approach here would be very costly in terms of bits. Is
> there some other way of dealing with this problem? Couldn't MyHDL just issue
> a warning?
>
>

You can not have multiple drivers if you wish to have a physical 
realization of the circuit.  The circuits are always driving their 
outputs, in the physical circuit -without including tri-states, mux, 
etc- there isn't the notion of not driving an output.  Depending on the 
type of source and sinks in the technology you could implement "wire 
and" and "wire or" but I am unaware of any tools (synthesis, par) that 
will support multiple drivers.

If you wish to have a physical realization of your circuit description 
you will need to define how the outputs are arbitrated.  This could be 
as simple as "or"ing the outputs together but it depends on your circuit.

Simulation allows multiple drivers so you can easily do things in 
testbenches, portions of the HDL that are not intended to be 
synthesized.  This is is the same in Verilog and VHDL.  Multiple drivers 
are not part of the synthesizable subset.  Even if MyHDL were to let 
this pass you would fail when you try and synthesize the underlying HDL.

Hope that helps,
Chris

Re: [myhdl-list] Signal has multiple drivers

[garyr <ga...@fi...>]

----- Original Message ----- 
From: "Christopher Felton" <chr...@gm...>
To: <myh...@li...>
Sent: Wednesday, November 23, 2011 9:09 AM
Subject: Re: [myhdl-list] Signal has multiple drivers


> On 11/22/11 6:29 PM, garyr wrote:
>> Code that appears to be OK when simulated produces errors "Signal has
>> multiple drivers" when I attempt to convert it to Verilog. In my case the
>> two drivers never access the signal at the same time so there should be
>> no
>> problem. Google didn't turn up any useful information.
>>
>> In one case a rather simple change eliminated the problem. Another
>> occurrence I eliminated by adding a multiplexer that routed a start and
>> an
>> 8-bit command signal to the shared module. A third occurrence involves an
>> unsigned division module having 32-bit parameters dividend, divisor and
>> quotient. The dividend and divisor signals would have multiple drivers.
>> Using a multiplexer approach here would be very costly in terms of bits.
>> Is
>> there some other way of dealing with this problem? Couldn't MyHDL just
>> issue
>> a warning?
>>
>>
>
> You can not have multiple drivers if you wish to have a physical
> realization of the circuit.  The circuits are always driving their
> outputs, in the physical circuit -without including tri-states, mux,
> etc- there isn't the notion of not driving an output.  Depending on the
> type of source and sinks in the technology you could implement "wire
> and" and "wire or" but I am unaware of any tools (synthesis, par) that
> will support multiple drivers.
>
> If you wish to have a physical realization of your circuit description
> you will need to define how the outputs are arbitrated.  This could be
> as simple as "or"ing the outputs together but it depends on your circuit.
>
> Simulation allows multiple drivers so you can easily do things in
> testbenches, portions of the HDL that are not intended to be
> synthesized.  This is is the same in Verilog and VHDL.  Multiple drivers
> are not part of the synthesizable subset.  Even if MyHDL were to let
> this pass you would fail when you try and synthesize the underlying HDL.
>
> Hope that helps,
> Chris
>
>
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It helped a lot. Thanks for the explanation.
Gary Richardson