On 10/10/2011 06:22 PM, Christopher Felton wrote:
> Not much thought or investigation behind this. But I notice today
> when converting a state-machine which used enum() for state
> definitions to VHDL, that I had to be careful with the names I chose.
> VHDL keywords and other VHDL naming rules had to be considered
> (obeyed).
>
> I had a state-machine I intended to convert to Verilog and VHDL but
> had only converted to Verilog. When I tried VHDL, D'oh. Simply, had
> to rename some of the states, like 'WAIT' and 'END' as well as
> removing trailing underscores (which were place-holders).
The mechanisms in the convertor to avoid name and keyword clashes
are broken (in the sense that they aren't present :-)).
I keep delaying it, because the problem is not that simple in
general. However, maybe we should do this in phases. Keyword checking
should be simple. What could be done:
* check for all keywords in VHDL/Verilog in the conversion.analyzer.
* issue an error for a keyword clash in the target conversion language,
and a warning for a keyword of the other one
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
World-class digital design: http://www.easics.com
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