myhdl-list

[myhdl-list] howto cite MyHDL

[Dan W. <eti...@gm...>]

I've used MyHDL for some digital parts on my last mixed-signal ASIC
for my PhD research.  The chip is currently in fab and I've been
waiting to get a die photo after testing to announce here the second
verified silicon using MyHDL in the flow.

However, we are writing up several papers related to the IC and are
not sure how to cite the software.  The place holder is:

"J. Decaluwe, 'MyHDL -- Python to Silicon,' http://www.myhdl.org"

Would a better reference be Jan's "MyHDL-based design of a digital
macro" paper or something else?

More info on the chip and thoughts after we verify the smoke stays in...

Thanks,
Dan White

Electrical Engineering
University of Nebraska-Lincoln

-- 
SDG
www.whiteaudio.com

Re: [myhdl-list] howto cite MyHDL

[Jan D. <ja...@ja...>]

On 10/03/2011 04:33 AM, Dan White wrote:
> I've used MyHDL for some digital parts on my last mixed-signal ASIC
> for my PhD research.  The chip is currently in fab and I've been
> waiting to get a die photo after testing to announce here the second
> verified silicon using MyHDL in the flow.

Congratulations, great news!

> However, we are writing up several papers related to the IC and are
> not sure how to cite the software.  The place holder is:
>
> "J. Decaluwe, 'MyHDL -- Python to Silicon,' http://www.myhdl.org"
>
> Would a better reference be Jan's "MyHDL-based design of a digital
> macro" paper or something else?

I would use the most appropriate reference for the context.

When referring to MyHDL in general, I would merely refer to the website
as the first source for more information. No names or taglines,
like one would do for VHDL or Verilog.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] howto cite MyHDL

[Christopher F. <chr...@gm...>]

On 10/2/11 9:33 PM, Dan White wrote:
> I've used MyHDL for some digital parts on my last mixed-signal ASIC
> for my PhD research.  The chip is currently in fab and I've been
> waiting to get a die photo after testing to announce here the second
> verified silicon using MyHDL in the flow.
>

Congratulations as well!  It seems MyHDL might have found a niche in 
mixed-signals ICs.

Regards,
Chris

Re: [myhdl-list] howto cite MyHDL

[Jan D. <ja...@ja...>]

On 10/05/2011 12:21 PM, Christopher Felton wrote:
> On 10/2/11 9:33 PM, Dan White wrote:
>> I've used MyHDL for some digital parts on my last mixed-signal ASIC
>> for my PhD research.  The chip is currently in fab and I've been
>> waiting to get a die photo after testing to announce here the second
>> verified silicon using MyHDL in the flow.
>>
>
> Congratulations as well!  It seems MyHDL might have found a niche in
> mixed-signals ICs.

 From what I see, this is becoming the niche of ASICs tout court:
pure digital designs are systematically migrating to FPGAs,
the few exceptions being super high volume and complexity designs.

Therefore - there must be some MyHDL FPGA success stories
out there as well. We may not have heard about them because
the typical ASIC milestones like sign-off and tape-out are
not applicable (fortunately I would add.) But I would encourage
anyone with such success stories (especially FPGAs in production)
to tell us about it if possible.

More than anything else, I think the project needs the
credibility from working silicon, FPGAs included.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] howto cite MyHDL

[Jan D. <ja...@ja...>]

On 10/06/2011 12:35 AM, Christopher Felton wrote:

> I will see if I can provide some details on the MyHDL designs I have
> fielded.  If not I will provide some generic descriptions in the
> user/project space.

Great, thanks. Once we have 4-5 projects, I propose to
add a "Silicon Success" page with the links, on a prominent
position on the website.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] MyHDL Success Stories

[Christopher F. <chr...@gm...>]

On 10/6/2011 12:14 PM, Jan Decaluwe wrote:
> On 10/06/2011 12:35 AM, Christopher Felton wrote:
>
>> I will see if I can provide some details on the MyHDL designs I have
>> fielded.  If not I will provide some generic descriptions in the
>> user/project space.
>
> Great, thanks. Once we have 4-5 projects, I propose to
> add a "Silicon Success" page with the links, on a prominent
> position on the website.
>
>

The following are commercial projects which I have used MyHDL.

1.  [FPGA] High-speed satellite communication link, NASA's TDRSS.  The 
modem was developed for the NASA's TKUP project while I was at RTLogic. 
  MyHDL was used for modeling and verification of high-speed DSP blocks.
http://www.rtlogic.com/press_releases/TKUP_Press_Release_8.31.07.pdf.

2.  [FPGA] Custom proprietary modem used over a non-common medium. 
MyHDL was used for modeling, verification, and implementation of a 
couple IP blocks.  This project is currently deployed in small numbers.

3.  [FPGA] MyHDL is used by DSPtronics.  These were small examples 
similar to the wiki space.  The platform was used by students at the 
University of Colorado, Colorado Springs (UCCS), 
http://www.eas.uccs.edu/wickert/ece4890/lecture_notes/ece4890_RFPs_Fa2011.pdf 
(note the overused graphic :) ).  I am not geographically located near 
this anymore (haven't been for 3 years), I am a little out of the loop. 
  I don't know how much has actually been done by the students (if any 
at all).  I don't know if this qualifies as a success story.

4.  [ASIC] Latest project, MyHDL was used for all verification of a 
digital subsystem in a mixed-signal IC.  The die have been received and 
are in the process of hardware testing.  I will be able to share more on 
this development in a couple months (maybe 6mos or more) after the 
research announcements/publications have been released.  In addition 
MyHDL was used completely to develop all logic for test/interface FPGA.

 From my perspective, MyHDL saved effort in developing and verifying 
these projects.  In the latest projects, kinda fallen into a nice flow, 
where:

   Tests and Test Infrastructure developed
   ASIC logic developed
   ASIC logic verified with test environment
     (post-syn and post-layout cosims)
   Final HW test fixture development
     FPGA logic, verified with previous test and design
   ASIC logic prototyped of FPGA (early FPGA proto to FW devs)
   Test fixture and prototype FPGA tested together
   Final hardware interface/tested with test-fixture

I liked this flow because it had multiple items cross checking each 
other as well as reuse.  The simulation test environment and FPGA test 
fixture are able to use the same Python test code.  As test code evolved 
it could be run against HDL simulations, FPGA prototype, and eventually 
final hardware.

Regards,
Chris

Re: [myhdl-list] howto cite MyHDL

[Christopher F. <chr...@gm...>]

On 10/5/11 9:58 AM, Jan Decaluwe wrote:
> On 10/05/2011 12:21 PM, Christopher Felton wrote:
>> On 10/2/11 9:33 PM, Dan White wrote:
>>> I've used MyHDL for some digital parts on my last mixed-signal ASIC
>>> for my PhD research.  The chip is currently in fab and I've been
>>> waiting to get a die photo after testing to announce here the second
>>> verified silicon using MyHDL in the flow.
>>>
>>
>> Congratulations as well!  It seems MyHDL might have found a niche in
>> mixed-signals ICs.
>
>    From what I see, this is becoming the niche of ASICs tout court:
> pure digital designs are systematically migrating to FPGAs,
> the few exceptions being super high volume and complexity designs.
>
True, very true, I agree.

> Therefore - there must be some MyHDL FPGA success stories
> out there as well. We may not have heard about them because
> the typical ASIC milestones like sign-off and tape-out are
> not applicable (fortunately I would add.) But I would encourage
> anyone with such success stories (especially FPGAs in production)
> to tell us about it if possible.
>
I will see if I can provide some details on the MyHDL designs I have 
fielded.  If not I will provide some generic descriptions in the 
user/project space.

> More than anything else, I think the project needs the
> credibility from working silicon, FPGAs included.
>

[myhdl-list] MyHDL Financial Industry Applications

[Christopher L. <loz...@fr...>]

Well I have wanted to do a parallel language on MyHDL for a while now,
but I was not able to find an application. 

Where is the money? In fast financial applications!  The problem is that
I do not know anyone in that industry.  I do not understand the
industry.   I need to go to a conference to get educated.

Here is the high performance computing conference in the Financial
Industry in New York in September.

http://www.flaggmgmt.com/hpc/index.html

Is anyone else interested in going?

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org