myhdl-list

[myhdl-list] From Python to Silicon: python-myhdl presentation

[Shakthi K. <sha...@gm...>]

Greetings!

I will be presenting python-myhdl at PyCon India 2011 [1]. Thanks to
Jan Decaluwe for his review, and code examples. The presentation is
available under CC BY-SA 3.0 [2].

The LaTeX Beamer sources of the presentation are available at gitorious.org [3].

I'd appreciate any feedback/suggestions regarding the presentation.

Thanks!

SK

[1] PyCon India 2011. http://in.pycon.org/

[2] From Python to Silicon: python-myhdl.
http://shakthimaan.com/downloads/glv/2011/pycon-2011/from-python-to-silicon.pdf

[3] Presentation git sources at gitorious.
https://gitorious.org/from-python-to-silicon/

-- 
Shakthi Kannan
http://www.shakthimaan.com

Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Christopher F. <chr...@gm...>]

On 9/15/2011 12:49 PM, Shakthi Kannan wrote:
> Greetings!
>
> I will be presenting python-myhdl at PyCon India 2011 [1]. Thanks to
> Jan Decaluwe for his review, and code examples. The presentation is
> available under CC BY-SA 3.0 [2].
>
> The LaTeX Beamer sources of the presentation are available at gitorious.org [3].
>
> I'd appreciate any feedback/suggestions regarding the presentation.
>
> Thanks!
>
> SK
>
> [1] PyCon India 2011. http://in.pycon.org/
>
> [2] From Python to Silicon: python-myhdl.
> http://shakthimaan.com/downloads/glv/2011/pycon-2011/from-python-to-silicon.pdf
>
> [3] Presentation git sources at gitorious.
> https://gitorious.org/from-python-to-silicon/
>

Given the presentation is mainly code snippets, there isn't much 
feedback to give other than: If the code snippets are incorrect or a 
suggestion for a better code snippet.  Neither I found or have.

I notice you have an hour for this presentation, I presume there will be 
a fair amount of dialogue accompanying the slides.  The topic I believe 
is interesting to this crowd is *why*?  Why is Python suitable for an 
HDL and why is it needed?

And this is where you start, illustrating generators and decorators. 
The Python flexibility and generality to become an HDL.  Additional 
information is available on Jan's "why" page, http://goo.gl/hoUKk.

Good luck, sounds like fun.  I believe someone presented MyHDL at 
pyIndia 2010 as well, http://goo.gl/FNm8P.

Penny short today, so this is my one cent opinion, which are mine and 
don't reflect the opinions of others (individuals or organizations) I am 
involved with.

Regards,
Chris Felton

Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Christopher F. <chr...@gm...>]

On 9/15/2011 12:49 PM, Shakthi Kannan wrote:
> Greetings!
>
> I will be presenting python-myhdl at PyCon India 2011 [1]. Thanks to
> Jan Decaluwe for his review, and code examples. The presentation is
> available under CC BY-SA 3.0 [2].
>
> The LaTeX Beamer sources of the presentation are available at gitorious.org [3].
>
> I'd appreciate any feedback/suggestions regarding the presentation.
>
> Thanks!
>
> SK
>
> [1] PyCon India 2011. http://in.pycon.org/
>
> [2] From Python to Silicon: python-myhdl.
> http://shakthimaan.com/downloads/glv/2011/pycon-2011/from-python-to-silicon.pdf
>
> [3] Presentation git sources at gitorious.
> https://gitorious.org/from-python-to-silicon/
>
(Guess I did have some more feedback)

The number of slides dedicated to explaining Gray code is a little 
excessive.  After the truth table slide, you can probably jump to slide 
20 (think it is 20).  And then jump to the last slide of the Gray table. 
  Explicitly walking through XOR of 0s is ... kinda ... yawn.

Unsigned and Signed Representation
-----------------------------------
I would show a signed and unsigned representation before converting 
(extending) an unsigned to a signed.
a = intbv(12, min=0, max=16)   # Unsigned
a = intbv(-12, min=0, max=16)  # What happens if unsigned to set sign
b = intbv(-12, min=16, max=16) # Signed
# Then conversion to signed

Unit Tests
-----------
Emphasize, this is one of the reasons why Python HDL *rules*.  You 
inherit the world of Python and its ecosystem and you don't have to 
reinvent the world -- unless that is what you do and you can convince 
your customers to pay for it :) --.

Conditional Instantiation
--------------------------
This might be a good spot (if not already discussed) the idea of the 
elaboration phase.  And those familiar with HDLs how this replaces the 
generates.

* Modeling
-----------
I think "Modeling" has been used in two different context and it might 
be confusing.  MyHDL can be used for a bunch of different purposes, 
including: (1) Modeling complex event based systems, (2) advanced 
verification/testbenches, and (3) as a convertible (synthesizable) HDL. 
  In these slides "Modeling" refers to items 1 and 3.

You use "RTL Modeling" for the generators that can be converted and 
plain "Modeling" for those that do not convert.  I would make additional 
effort to make sure this is clear when presenting.

I guess this is the same for the "Structural Modeling", in the 
discussion make clear the "structural" and "RTL" are convertible and the 
other "modeling" is not.

Intermediate Summary (So far have learned)
------------------------------------------
Before the PyPy you might want a quick summary to this point.
   * Describe the HDL in Python/MyHDL
   * Simulate
   * Convert to Verilog or VHDL
   * Co-simulate to verify conversion correctness
   * Synthesize to target technology
   * Co-simulate with synthesized netlist

Using PyPy
-----------
Since these tables are directly from Jan's wikipage I would add the 
reference to this slide.  Indicate where the info was taken.  Also, it 
would be nice to see this table in a normalized percentage.  You could 
normalize to MyHDL@pypy or Normalize to one of the others, example.

MPyPy_Compare
Out[364]:
{'findmax': {'ghdl': 2256, 'iver': 56, 'pypy': 86,
              'ver1': 21, 'vhdl1': 37},
  'lfsr24': {'ghdl': 71, 'iver': 79, 'pypy': 66,
             'ver1': 266, 'vhdl1': 240},
  'logdiv': {'ghdl': 224, 'iver': 43, 'pypy': 69,
             'ver1': 96, 'vhdl1': 98},
  'randgen': {'ghdl': 24, 'iver': 197, 'pypy': 62,
              'ver1': 76, 'vhdl1': 67},
  'timer': {'ghdl': 146, 'iver': 106, 'pypy': 62,
            'ver1': 260, 'vhdl1': 219}}

for k,v in MPyPy_Compare.items():
     print("%8s : %1.2f | %1.2f | %1.2f | %1.2f | %1.2f" % (k,
           v['pypy']/float(v['iver']),
           v['iver']/float(v['iver']),
           v['ghdl']/float(v['iver']),
           v['ver1']/float(v['iver']),
           v['vhdl1']/float(v['iver']) )
)

    timer : 0.58 | 1.00 | 1.38  | 2.45 | 2.07
   lfsr24 : 0.84 | 1.00 | 0.90  | 3.37 | 3.04
  randgen : 0.31 | 1.00 | 0.12  | 0.39 | 0.34
   logdiv : 1.60 | 1.00 | 5.21  | 2.23 | 2.28
  findmax : 1.54 | 1.00 | 40.29 | 0.38 | 0.66

The above normalized to Icarus.  Or you could normalize to pypy and see 
how the others compare.

    timer : 1.00 | 1.71 | 2.35  | 4.19 | 3.53
   lfsr24 : 1.00 | 1.20 | 1.08  | 4.03 | 3.64
  randgen : 1.00 | 3.18 | 0.39  | 1.23 | 1.08
   logdiv : 1.00 | 0.62 | 3.25  | 1.39 | 1.42
  findmax : 1.00 | 0.65 | 26.23 | 0.24 | 0.43

I guess, normalizing to pypy is the most dramatic and gets the 
information across the fastest, IMO.

Regards,
Chris Felton

Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Shakthi K. <sha...@gm...>]

Hi Christopher:

--- On Fri, Sep 16, 2011 at 8:19 PM, Christopher Felton
<chr...@gm...> wrote:
| The number of slides dedicated to explaining Gray code is a little
| excessive.  After the truth table slide, you can probably jump to slide
| 20 (think it is 20).  And then jump to the last slide of the Gray table.
|  Explicitly walking through XOR of 0s is ... kinda ... yawn.
\--

:) There will be quite a few students in the audience, and I don't
want them to ponder on the logic as to how it works. Hence, the
explicit walk through. Others can just skip through that part.

The manual is well documented, so I didn't want to repeat the same in
the presentation. Moreover, the focus is on how Python and
python-myhdl is useful for HDL. Hence, just the code examples and
illustrations.

---
| I would show a signed and unsigned representation before converting
| (extending) an unsigned to a signed.
| a = intbv(12, min=0, max=16)   # Unsigned
| a = intbv(-12, min=0, max=16)  # What happens if unsigned to set sign
| b = intbv(-12, min=16, max=16) # Signed
| # Then conversion to signed
\--

For "a = intbv(-12, min=0, max=16)", how can we set value to -12, when
minimum is 0? Same with "b = intbv(-12, min=16, max=16)". These return
a ValueError.

Can you elaborate on what you would like to emphasize here?

---
| Unit Tests
| -----------
| Emphasize, this is one of the reasons why Python HDL *rules*.  You
| inherit the world of Python and its ecosystem and you don't have to
| reinvent the world -- unless that is what you do and you can convince
| your customers to pay for it :) --.
\--

True :)

---
| I guess this is the same for the "Structural Modeling", in the
| discussion make clear the "structural" and "RTL" are convertible and the
| other "modeling" is not.
\--

I have now explicitly mentioned "High Level Modelling" for the sparse
memory and fifo examples at:

  http://www.myhdl.org/doc/current/manual/modeling.html#high-level-modeling

---
| Before the PyPy you might want a quick summary to this point.
|   * Describe the HDL in Python/MyHDL
|   * Simulate
|   * Convert to Verilog or VHDL
|   * Co-simulate to verify conversion correctness
|   * Synthesize to target technology
|   * Co-simulate with synthesized netlist
\--

Yes, I have demos for the examples, and will use them during the presentation.

---
| Using PyPy
| -----------
| Since these tables are directly from Jan's wikipage I would add the
| reference to this slide.
\--

Updated.

---
| Also, it
| would be nice to see this table in a normalized percentage.  You could
| normalize to MyHDL@pypy or Normalize to one of the others, example.
|
| Or you could normalize to pypy and see
| how the others compare.
|
| I guess, normalizing to pypy is the most dramatic and gets the
| information across the fastest, IMO.
\--

Updated. Thanks for your feedback!

SK

-- 
Shakthi Kannan
http://www.shakthimaan.com

Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Christopher F. <chr...@gm...>]

On 9/16/2011 11:17 AM, Shakthi Kannan wrote:
> Hi Christopher:
>
> --- On Fri, Sep 16, 2011 at 8:19 PM, Christopher Felton
> <chr...@gm...>  wrote:
> | The number of slides dedicated to explaining Gray code is a little
> | excessive.  After the truth table slide, you can probably jump to slide
> | 20 (think it is 20).  And then jump to the last slide of the Gray table.
> |  Explicitly walking through XOR of 0s is ... kinda ... yawn.
> \--
>
> :) There will be quite a few students in the audience, and I don't
> want them to ponder on the logic as to how it works. Hence, the
> explicit walk through. Others can just skip through that part.

Sure, it is ok.  But, my opinion, you only need to show 0+0=0 once, and 
you can jump ahead.  But no foul no harm.

>
> The manual is well documented, so I didn't want to repeat the same in
> the presentation. Moreover, the focus is on how Python and
> python-myhdl is useful for HDL. Hence, just the code examples and
> illustrations.

This feeds an argument against the explicit logic walk through because, 
as you said, the focus is Python and Python-MyHDL, IMO.

>
> ---
> | I would show a signed and unsigned representation before converting
> | (extending) an unsigned to a signed.
> | a = intbv(12, min=0, max=16)   # Unsigned
> | a = intbv(-12, min=0, max=16)  # What happens if unsigned to set sign
> | b = intbv(-12, min=16, max=16) # Signed
> | # Then conversion to signed
> \--
>
> For "a = intbv(-12, min=0, max=16)", how can we set value to -12, when
> minimum is 0? Same with "b = intbv(-12, min=16, max=16)". These return
> a ValueError.
>
> Can you elaborate on what you would like to emphasize here?

That is the point, a negative value assigned to an unsigned causes a 
value error (you won't see this in Verilog).  You need the correct 
bounds to represent a number.  Failing examples are as useful as correct 
examples.

>
> ---
> | Unit Tests
> | -----------
> | Emphasize, this is one of the reasons why Python HDL *rules*.  You
> | inherit the world of Python and its ecosystem and you don't have to
> | reinvent the world -- unless that is what you do and you can convince
> | your customers to pay for it :) --.
> \--
>
> True :)
>
> ---
> | I guess this is the same for the "Structural Modeling", in the
> | discussion make clear the "structural" and "RTL" are convertible and the
> | other "modeling" is not.
> \--
>
> I have now explicitly mentioned "High Level Modelling" for the sparse
> memory and fifo examples at:
>
>    http://www.myhdl.org/doc/current/manual/modeling.html#high-level-modeling

Cool, I think that works, stating the different types of modeling, 
Structural, RTL, and HL.

>
> ---
> | Before the PyPy you might want a quick summary to this point.
> |   * Describe the HDL in Python/MyHDL
> |   * Simulate
> |   * Convert to Verilog or VHDL
> |   * Co-simulate to verify conversion correctness
> |   * Synthesize to target technology
> |   * Co-simulate with synthesized netlist
> \--
>
> Yes, I have demos for the examples, and will use them during the presentation.

That isn't what I was thinking.  I was thinking a slide that summarizes 
up to the point (just before the pypy) will be a better transition to 
the pypy information.  Summarizing the design flow is one possibility.

>
> ---
> | Using PyPy
> | -----------
> | Since these tables are directly from Jan's wikipage I would add the
> | reference to this slide.
> \--
>
> Updated.
>
> ---
> | Also, it
> | would be nice to see this table in a normalized percentage.  You could
> | normalize to MyHDL@pypy or Normalize to one of the others, example.
> |
> | Or you could normalize to pypy and see
> | how the others compare.
> |
> | I guess, normalizing to pypy is the most dramatic and gets the
> | information across the fastest, IMO.
> \--
>
> Updated. Thanks for your feedback!
>
> SK
>

No problem, have fun.

Chris Felton

Re: [myhdl-list] From Python to Silicon: python-myhdl presentation

[Shakthi K. <sha...@gm...>]

Hi Christopher:

--- On Fri, Sep 16, 2011 at 11:35 PM, Christopher Felton
<chr...@gm...> wrote:
| This feeds an argument against the explicit logic walk through because,
| as you said, the focus is Python and Python-MyHDL, IMO.
\--

Yes, it is an exception. I found all the examples from the manual to
be simple and easy to follow except for the reasoning behind using the
XOR for the bin2gray example. Hence, the need for the explicit logic
walk.

---
| That is the point, a negative value assigned to an unsigned causes a
| value error (you won't see this in Verilog).  You need the correct
| bounds to represent a number.  Failing examples are as useful as correct
| examples.
\--

Makes sense! Will include them.

---
|  I was thinking a slide that summarizes
| up to the point (just before the pypy) will be a better transition to
| the pypy information.  Summarizing the design flow is one possibility.
\--

Will include this. Thanks for your feedback and prompt replies. Appreciate it!

SK

-- 
Shakthi Kannan
http://www.shakthimaan.com