On Thu, Jun 16, 2011 at 11:57, Sadique Sheik <sa...@in...> wrote:
> Hi,
>
> I am absolutely new to HDL (just started 3 weeks ago!).
>
> I started with some reading on VHDL but fell in love with MyHDL.
> I have been trying to do some basic simulations where i use a simple
> RAM. I basically copied it from the documentation.
> http://www.myhdl.org/doc/0.6/manual/conversion_examples.html#ram-inference
>
> Now in my simulation i use the addr signal in more than one location to
> read from the ram. While simulating, everything works as expected. But
> when i try conversion to VHDL it complains :
>
> Signal has multiple drivers: addr
>
What he means there, is that in your current design, multiple source
can set the value of the `addr` signal. While this may go well in your
simulation process (for instance, because you care that only one
source at a time tries to set it), the convertor cannot make sure that
it will always work and for this reason ask you to reduce the number
of soures to 1.
> A bit of googling on this issue tells me that I should either set the
> signal to "tristate" while i am not using it or use a "resolution
> function."
>
> A quick search in MyHDL documentation tells me that tristate thing is
> not a very nice thing to do. Can some one tell me how this is usually
> handled ?
>
> Can I get an example on how to define and use a "resolution function".
A resolution function, sometimes also called `arbiter`, will care
about setting the value of the `addr` signal. Thus he will be the only
one writing to this signal. The input of this module will consists of
all the whished `addr` values from all the modules trying to set it,
*and* a synchronisation mechanism that will instruct the arbiter who
tries to set the `addr` value. Those might go from very simple to
quite elaborated, depending on your design.
The easiest sample of such an arbiter is a multiplexer:
def mux2(addr1, addr2, sel, addr):
@always_comb:
def muxLogic():
addr.next = addr1
if sel == 1:
addr.next = addr2
return muxLogic
But as said, such module can become really complicated.
In the case of your RAM, a common seen practice is to have two `raddr`
(read address) input in you module and two associated `dout` (data
output) allowing two simultaneous read to happen from different
modules.
Hope this helps.
Regards
Benoît.
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