myhdl-list

[myhdl-list] Using MyHDL with existing infrastructure

[glenn <jon...@ca...>]

Hello,
Currently I use Simulink with Xilinx System Generator to generate DSP designs 
in VHDL which I then use in a board with well defined peripherals and an
FPGA-PowerPC interface for setting/reading registers on the FPGA. To do this,
I have scripts that automatically generate a PCORE from the XSG design by
generating the necessary bbd and mpd files. The bbd file is trivial to 
generate.
To generate the mpd, which contains information about the top level ports of
the design, the tools are able to figure out the top level ports of the 
Simulink design. Special blocks are used to represent signals that should be
connected to the PowerPC bus. These blocks wrap the "gateway in/out" blocks 
that are used to instantiate a top level port.

I've taken a brief look at the code used by the toVHDL function, and it 
seems like it should be possible to do something similar. One way might be to 
define a subclass of Signal that when encountered by the analyzer provides 
information for the mpd file, but otherwise acts just like a normal signal.

One important aspect I'd like to preserve is the ability to place a top 
level port intended to be connected to the PowerPC deep within the 
hierarchy of the design without having to bring the signals all the 
way to the top level explicitly. I haven't seen a way to do this in 
MyHDL, but it seems like it should be possible since the resulting 
VHDL ends up with a flattened hierarchy anyway.

I appreciate any suggestions. I'm happy to clarify anything that 
might be confusing.

Thanks in advance,
Glenn

Re: [myhdl-list] Using MyHDL with existing infrastructure

[Christopher F. <chr...@gm...>]

<snip>
>
> One important aspect I'd like to preserve is the ability to place a top
> level port intended to be connected to the PowerPC deep within the
> hierarchy of the design without having to bring the signals all the
> way to the top level explicitly. I haven't seen a way to do this in
> MyHDL, but it seems like it should be possible since the resulting
> VHDL ends up with a flattened hierarchy anyway.
>
> I appreciate any suggestions. I'm happy to clarify anything that
> might be confusing.
>
> Thanks in advance,
> Glenn
>

Here is a small example to achieve what (I think) you are describing. 
More information can be found here,
http://www.myhdl.org/doc/current/manual/conversion_examples.html#conv-usage-custom

from myhdl import *

def BurriedInstance(clk, rst, data_in, data_out):

     # ... Some Code
     bi = nativeInstance(clk, rst, data_in, data_out)
     # ... Some More Code

     return bi  #other generators

def nativeInstance(clk, rst, data_in, data_out):

     @always(clk, rst, data_in)
     def pass_thru():
         pass
     data_out.driven = "wire"

     nativeInstance.vhdl_code = """
     P1:ppc port map($clk, $rst, $data_in, $data_out);
     """

     return pass_thru


if __name__ == '__main__':
     clk = Signal(False)
     rst = Signal(False)
     data_in  = Signal(intbv(0)[8:])
     data_out = Signal(intbv(0)[8:])
     toVHDL(BurriedInstance, clk, rst, data_in, data_out)


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Re: [myhdl-list] Using MyHDL with existing infrastructure

[Christopher F. <chr...@gm...>]

On 6/2/2011 8:01 AM, Christopher Felton wrote:
> <snip>
>>
>> One important aspect I'd like to preserve is the ability to place a top
>> level port intended to be connected to the PowerPC deep within the
>> hierarchy of the design without having to bring the signals all the
>> way to the top level explicitly. I haven't seen a way to do this in
>> MyHDL, but it seems like it should be possible since the resulting
>> VHDL ends up with a flattened hierarchy anyway.
>>
<snip>
>       toVHDL(BurriedInstance, clk, rst, data_in, data_out)
>
(d'oh, hit send to early)

You will need the latest MyHDL release (0.7).  The only issue might be 
running MyHDL simulations.  You might want to use the __debug__ and 
define some simple logic to enable MyHDL simulations.

Below is a snippet of the VHDL generated:

architecture MyHDL of BurriedInstance is
begin
     P1:ppc port map(clk, rst, data_in, data_out);

end architecture MyHDL;

Regards,
Chris Felton