Thread: [myhdl-list] rosettacode submission
Brought to you by:
jandecaluwe
Menu
▾
▴
myhdl-list
|
From: Jan C. <jan...@mu...> - 2011-03-19 12:08:01
Attachments:
Four_bit_adder_intbv05.py
|
While helping with some code debugging for another rosettacode page, I noticed that there is a simple hardware category: http://rosettacode.org/wiki/Four_bit_adder I now have some questions about my potential submission: 1) Could posting this on rosettacode generate an unwelcome influx of MyHDL newbies? 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed something, or do I have to use an @always_comb and loop? 3) Does my code have about the right level of commenting for a novice reader? Should I expand signal names for easier reading? Any further suggestions for making this submission attractive, understandable, and a good representation of MyHDL would be much appreciated. Jan Coombs |
|
From: Felton C. <chr...@gm...> - 2011-03-21 03:36:29
|
On Mar 19, 2011, at 7:07 AM, Jan Coombs wrote: > While helping with some code debugging for another rosettacode page, > I noticed that there is a simple hardware category: > > .0200 > > I now have some questions about my potential submission: > > 1) Could posting this on rosettacode generate an unwelcome influx of > MyHDL newbies? I would not be concerned about this. > > 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed > something, or do I have to use an @always_comb and loop? I am not familiar with *reversed? Will need to look at this when I have some time. > > 3) Does my code have about the right level of commenting for a > novice reader? Should I expand signal names for easier reading? I think it is fine but I would use the port names defined on the rossetta page. That makes it easier to follow for someone working through the page. > > Any further suggestions for making this submission attractive, > understandable, and a good representation of MyHDL would be much > appreciated. > > Jan Coombs Couple additional comments, I would add self-checking capabilities to the testbench vs. simply printing out the results. Also, I know this example follows the page description for a "simulation" on the rosetta code page (your code has the comment "synthesis"?). Instead of a bottom up approach I think it would be nice to show an actual "behavioral" synthesis and show that the tools generate the full-adder as described. In my opinion, other than an academic exercise, creating a the 4-bit adder built from HA and FAs has limited use. I do realize that is probably not the intent of the example for the page. Some of the other examples don't create functions/modules for the primitive operations. It makes the example very explicit but with that it is verbose. Chris Felton |
|
From: Jan D. <ja...@ja...> - 2011-03-21 11:33:04
|
I believe the most important thing is to look good :-) I don't think we should be holier than the pope - ADA and SystemVerilog in this case. Both use basic bit-operations to model basic gates - even an xor as opposed to what the spec says. We should be allowed to do the same and start from the Half-Adder. I would keep things simple and first do the whole thing using lists of signals. Then, I would use a top-level wrapper that would only do the conversion from intbv's to lists and vice versa. Note that, in a real design environment, this is only strictly necessary if you want to convert the adder as a top-level - something not very likely. The ConcatSignal in your code really creates a signal and should be used outside generators, if conversion is an issue (and probably otherwise also, to use Signals in the "intended" way.) The functional equivalent that returns a value is myhdl.concat. I would *definitely* include a simple test bench, using `assert` that could be used by a framework such as py.test. Jan On 03/19/2011 01:07 PM, Jan Coombs wrote: > While helping with some code debugging for another rosettacode page, I noticed that there is a simple hardware category: > > http://rosettacode.org/wiki/Four_bit_adder > > I now have some questions about my potential submission: > > 1) Could posting this on rosettacode generate an unwelcome influx of MyHDL newbies? > > 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed something, or do I have to use an @always_comb and loop? > > 3) Does my code have about the right level of commenting for a novice reader? Should I expand signal names for easier reading? > > Any further suggestions for making this submission attractive, understandable, and a good representation of MyHDL would be much appreciated. > > Jan Coombs > > > > ------------------------------------------------------------------------------ > Colocation vs. Managed Hosting > A question and answer guide to determining the best fit > for your organization - today and in the future. > http://p.sf.net/sfu/internap-sfd2d > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |
|
From: Jan D. <ja...@ja...> - 2011-03-21 19:10:46
Attachments:
Multibit_Adder.py
|
I couldn't resist to post my take on this. I realize that the whole handling of lists is sometimes confusing, however I think that is especially so for small examples like this with a "forced" structural approach. I have added comments to clarify what I'm doing. I would use the opportunity to illustrate conversion to Verilog and VHDL, and unit testing. This is all in my example code. I have used the SystemVerilog code as an example - the unit test worked first time right. On 03/21/2011 12:32 PM, Jan Decaluwe wrote: > I believe the most important thing is to look good :-) > > I don't think we should be holier than the pope - ADA and > SystemVerilog in this case. Both use basic bit-operations > to model basic gates - even an xor as opposed to what > the spec says. We should be allowed to do the same and > start from the Half-Adder. > > I would keep things simple and first do the whole thing > using lists of signals. Then, I would use a top-level wrapper > that would only do the conversion from intbv's to lists and vice > versa. Note that, in a real design environment, this is only > strictly necessary if you want to convert the adder as > a top-level - something not very likely. > > The ConcatSignal in your code really creates a signal and should > be used outside generators, if conversion is an issue > (and probably otherwise also, to use Signals in the "intended" way.) > The functional equivalent that returns a value is myhdl.concat. > > I would *definitely* include a simple test bench, using `assert` > that could be used by a framework such as py.test. > > Jan > > On 03/19/2011 01:07 PM, Jan Coombs wrote: >> While helping with some code debugging for another rosettacode page, I noticed that there is a simple hardware category: >> >> http://rosettacode.org/wiki/Four_bit_adder >> >> I now have some questions about my potential submission: >> >> 1) Could posting this on rosettacode generate an unwelcome influx of MyHDL newbies? >> >> 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed something, or do I have to use an @always_comb and loop? >> >> 3) Does my code have about the right level of commenting for a novice reader? Should I expand signal names for easier reading? >> >> Any further suggestions for making this submission attractive, understandable, and a good representation of MyHDL would be much appreciated. >> >> Jan Coombs >> >> >> >> ------------------------------------------------------------------------------ >> Colocation vs. Managed Hosting >> A question and answer guide to determining the best fit >> for your organization - today and in the future. >> http://p.sf.net/sfu/internap-sfd2d >> >> >> >> _______________________________________________ >> myhdl-list mailing list >> myh...@li... >> https://lists.sourceforge.net/lists/listinfo/myhdl-list > > -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |
|
From: Jan C. <jan...@mu...> - 2011-03-21 23:34:38
|
On 21/03/11 19:10, Jan Decaluwe wrote: > I couldn't resist to post my take on this. . . . Thanks, much appreciated. I had started to take on board Chris and your comments, but still have much to learn. As to what to post on rosettacode I have asked for guidance from the problem proposer. Should David Blubaugh and myself go ahead with the goal of producing a novel processor core using MyHDL, what level of traffic would be welcome here? Jan Coombs |
|
From: Christopher F. <cf...@uc...> - 2011-03-22 12:58:03
|
On Mon, Mar 21, 2011 at 6:34 PM, Jan Coombs < jan...@mu...> wrote: > On 21/03/11 19:10, Jan Decaluwe wrote: > > I couldn't resist to post my take on this. . . . > Thanks, much appreciated. I had started to take on board Chris and > your comments, but still have much to learn. As to what to post on > rosettacode I have asked for guidance from the problem proposer. > > Should David Blubaugh and myself go ahead with the goal of > producing a novel processor core using MyHDL, what level of traffic > would be welcome here? > > In my opinion, any level of activity would be fine. But you might find that responses and activity will vary. If you are expecting to get frequent response in minutes or hours, you might be disappointed. But I think you will get some type of response / comment within a couple of days. If the participants are ok with the described expectations, post away! Chris Felton |
|
From: David B. <dav...@ya...> - 2011-03-23 20:52:11
|
Jan, I will be more than happy to be apart of the project. David Blubaugh --- On Mon, 3/21/11, Jan Coombs <jan...@mu...> wrote: From: Jan Coombs <jan...@mu...> Subject: Re: [myhdl-list] rosettacode submission To: myh...@li... Date: Monday, March 21, 2011, 7:34 PM On 21/03/11 19:10, Jan Decaluwe wrote: > I couldn't resist to post my take on this. . . . Thanks, much appreciated. I had started to take on board Chris and your comments, but still have much to learn. As to what to post on rosettacode I have asked for guidance from the problem proposer. Should David Blubaugh and myself go ahead with the goal of producing a novel processor core using MyHDL, what level of traffic would be welcome here? Jan Coombs ------------------------------------------------------------------------------ Enable your software for Intel(R) Active Management Technology to meet the growing manageability and security demands of your customers. Businesses are taking advantage of Intel(R) vPro (TM) technology - will your software be a part of the solution? Download the Intel(R) Manageability Checker today! http://p.sf.net/sfu/intel-dev2devmar _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
|
From: Christopher F. <chr...@gm...> - 2011-03-23 21:14:55
|
Jan D. has created project spaces on the MyHDL wiki. You can create a page for this project. Others might be interested in the progress and development. It will also be a good place to post non-text information (block diagrams, etc) that might be useful in newsgroup conversations. Chris Felton On Wed, Mar 23, 2011 at 3:52 PM, David Blubaugh <dav...@ya... > wrote: > Jan, > > I will be more than happy to be apart of the project. > > David Blubaugh > > > > > --- On *Mon, 3/21/11, Jan Coombs <jan...@mu...>*wrote: > > > From: Jan Coombs <jan...@mu...> > Subject: Re: [myhdl-list] rosettacode submission > To: myh...@li... > Date: Monday, March 21, 2011, 7:34 PM > > > On 21/03/11 19:10, Jan Decaluwe wrote: > > I couldn't resist to post my take on this. . . . > Thanks, much appreciated. I had started to take on board Chris and > your comments, but still have much to learn. As to what to post on > rosettacode I have asked for guidance from the problem proposer. > > Should David Blubaugh and myself go ahead with the goal of > producing a novel processor core using MyHDL, what level of traffic > would be welcome here? > > Jan Coombs > > > |
|
From: Christopher F. <chr...@gm...> - 2011-04-02 13:45:50
|
On 3/21/11 6:34 PM, Jan Coombs wrote: > On 21/03/11 19:10, Jan Decaluwe wrote: >> I couldn't resist to post my take on this. . . . > Thanks, much appreciated. I had started to take on board Chris and > your comments, but still have much to learn. As to what to post on > rosettacode I have asked for guidance from the problem proposer. > > I was curious if something was submitted to rosettacode? Jan D. version could be submitted. Chris Felton |
|
From: Jan C. <jan...@mu...> - 2011-04-02 16:54:27
|
On 02/04/11 14:45, Christopher Felton wrote: > I was curious if something was submitted to rosettacode? Jan D. version > could be submitted. I wrote to Mauro Panigada, who set this challenge, asking for guidance as to what to post. Although I was not surprised that he wanted my school-homework style solution, I intended to clean it up first. Perhaps I should just post both. Jan Coombs -- Mauro Panigada wrote: I think it is very interesting, I will take a deeper look in my spare time! Quickly viewing the attached sources, it seems to me your solution meets task requirements; post your own solution on RC, if you've not done so already, this is my only advice:) About giving MyHDL its own category, I disagree: after all, it is Python exploiting Python's capabilities, packages and so on. So I believe it is enough to use the libheader "tag" (or similar, but if I remember well RC still does not distinguish among libraries in the "C meaning" and libraries/packages/modules/whatever in "other language meaning"). However, comments page on RC are also to discuss this kind of topic, and there are a lot of persons there that likely would disagree with me. Thanks you for having brought to my attention MyHDL! It's that sort of thing I like a lot (though currently I've drifted mainly to musical composition in my spare time, just to break with programming a bit --- but hardware design is still in my mind :D) Have a good day (here in Italy it's 7:30 AM) On Mon, Mar 21, 2011 at 11:48 PM, Jan <jan...@mu...> wrote: > > hi Mauro, > > > > I have tackled this problem using MyHDL (myhdl.org), a python library > > which is designed for hardware simulation. > > > > Attached is my very structured solution, also the solution of the author of > > MyHDL. I'm not sure which approach meets your illustrative goal better, and > > would like advice. > > > > MyHDL meets a number of your mentioned future goals, being able to > > represent clocks and latches, and is also capable of exporting VHDL or > > Verilog for real hardware design. > > > > Because of the capabilities of MyHDL, I think that it should have a > > separate language category in RC, rather than being combined with python, > > what do you think? > > > > Kind regards, Jan Coombs. > > > > |
|
From: Jan D. <ja...@ja...> - 2011-04-02 17:49:32
|
On 04/02/2011 06:53 PM, Jan Coombs wrote: > On 02/04/11 14:45, Christopher Felton wrote: >> I was curious if something was submitted to rosettacode? Jan D. version >> could be submitted. > > I wrote to Mauro Panigada, who set this challenge, asking for > guidance as to what to post. Although I was not surprised that he > wanted my school-homework style solution, I intended to clean it up > first. Perhaps I should just post both. I read that he doesn't agree to give MyHDL it own category. That would mean to miss the point completely, and I recommend not to send the code until he reconsiders. The fact that MyHDL is "pure Python" is a (hopefully clever) design choice. It doesn't mean that someone with only Python background and no hardware experience will understand the essence of what is going on. Unless we get our own category, I fear we will not get the message accross, and we are wasting efforts. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |
|
From: Jan C. <jan...@mu...> - 2011-05-09 11:24:55
|
On 02/04/11 18:49, Jan Decaluwe wrote: > . . . > I read that he doesn't agree to give MyHDL it own category. Does this look like a good compromise? http://rosettacode.org/wiki/Four_bit_adder#MyHDL Any other comments? Jan Coombs |
|
From: Christopher F. <chr...@gm...> - 2011-05-09 11:34:42
|
On 5/9/2011 6:24 AM, Jan Coombs wrote: > On 02/04/11 18:49, Jan Decaluwe wrote: >> . . . >> I read that he doesn't agree to give MyHDL it own category. > > Does this look like a good compromise? > > http://rosettacode.org/wiki/Four_bit_adder#MyHDL > > Any other comments? > > Jan Coombs I thought a separate section for MyHDL would not be provided/added? I still do not prefer the structural approach. I think the inverter, and2, or2, xor2 should be removed and the operators simply used. Chris |
|
From: Jan C. <jan...@mu...> - 2011-05-09 11:57:51
|
On 09/05/11 12:34, Christopher Felton wrote: > On 5/9/2011 6:24 AM, Jan Coombs wrote: >> On 02/04/11 18:49, Jan Decaluwe wrote: >>> . . . >>> I read that he doesn't agree to give MyHDL it own category. >> >> Does this look like a good compromise? >> >> http://rosettacode.org/wiki/Four_bit_adder#MyHDL >> >> Any other comments? >> >> Jan Coombs > > I thought a separate section for MyHDL would not be provided/added? > > I still do not prefer the structural approach. I think the inverter, > and2, or2, xor2 should be removed and the operators simply used. Well, compromises are difficult!:) Because I agree with you I posted both my solution and Jan D's. The proposer of the problem spec said that the verbose version met his goals best, so I put mine first. He also said that MyHDL did not warrant a separate language section, which Jan & I believe is incorrect, so I created a new language section. I hope that more hardware teaching problems are proposed on rosettacode, and that further suitable dual style solutions are posted. Jan Coombs |
|
From: Christopher F. <chr...@gm...> - 2011-05-09 12:16:23
|
On 5/9/2011 6:57 AM, Jan Coombs wrote: > On 09/05/11 12:34, Christopher Felton wrote: >> On 5/9/2011 6:24 AM, Jan Coombs wrote: >>> On 02/04/11 18:49, Jan Decaluwe wrote: >>>> . . . >>>> I read that he doesn't agree to give MyHDL it own category. >>> >>> Does this look like a good compromise? >>> >>> http://rosettacode.org/wiki/Four_bit_adder#MyHDL >>> >>> Any other comments? >>> >>> Jan Coombs >> >> I thought a separate section for MyHDL would not be provided/added? >> >> I still do not prefer the structural approach. I think the inverter, >> and2, or2, xor2 should be removed and the operators simply used. > > Well, compromises are difficult!:) Because I agree with you I > posted both my solution and Jan D's. > > The proposer of the problem spec said that the verbose version met > his goals best, so I put mine first. > > He also said that MyHDL did not warrant a separate language > section, which Jan& I believe is incorrect, so I created a new > language section. > > I hope that more hardware teaching problems are proposed on > rosettacode, and that further suitable dual style solutions are posted. > > Jan Coombs Thanks for the explanation. I did not notice the second version. Chris |
|
From: Jan D. <ja...@ja...> - 2011-03-21 11:35:19
|
I believe the most important thing is to look good :-) I don't think we should be holier than the pope - ADA and SystemVerilog in this case. Both use basic bit-operations to model basic gates - even an xor as opposed to what the spec says. We should be allowed to do the same and start from the Half-Adder. I would keep things simple and first do the whole thing using lists of signals. Then, I would use a top-level wrapper that would only do the conversion from intbv's to lists and vice versa. Note that, in a real design environment, this is only strictly necessary if you want to convert the adder as a top-level - something not very likely. The ConcatSignal in your code really creates a signal and should be used outside generators, if conversion is an issue (and probably otherwise also, to use Signals in the "intended" way.) The functional equivalent that returns a value is myhdl.concat. I would *definitely* include a simple test bench, using `assert` that could be used by a framework such as py.test. Jan On 03/19/2011 01:07 PM, Jan Coombs wrote: > While helping with some code debugging for another rosettacode page, I noticed that there is a simple hardware category: > > http://rosettacode.org/wiki/Four_bit_adder > > I now have some questions about my potential submission: > > 1) Could posting this on rosettacode generate an unwelcome influx of MyHDL newbies? > > 2) My 'ConcatSignal(*reversed' phrase did not work. Have I missed something, or do I have to use an @always_comb and loop? > > 3) Does my code have about the right level of commenting for a novice reader? Should I expand signal names for easier reading? > > Any further suggestions for making this submission attractive, understandable, and a good representation of MyHDL would be much appreciated. > > Jan Coombs > > > > ------------------------------------------------------------------------------ > Colocation vs. Managed Hosting > A question and answer guide to determining the best fit > for your organization - today and in the future. > http://p.sf.net/sfu/internap-sfd2d > > > > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |
×
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.
Thanks for helping keep SourceForge clean.
X